Texas Instruments 的 TLC59482 規格書

I TEXAS INSTRUMENTS
¼
SIN
SCLK
LAT
GSCLK
SOUT
GND
VCC
Device 1 VCC
¼
¼
¼
SIN
SCLK
LAT
GSCLK
RIREF
IREF
SOUT
Device n
OUT0 OUT15
DATA
SCLK
GSCLK
¼
RIREF
IREF
Controller GND
VCC
VCC
3
LAT
¼
¼
OUT0 OUT15
¼
DataRead
VLED
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
16-Channel, 16-Bit, PWM LED Driver with
6-Bit Global Brightness Control
Check for Samples: TLC59482
1FEATURES APPLICATIONS
2• 16 Constant-Current Sink Output Channels • LED Video Displays
• Sink Current Capability with Max BC Data: • LED Signboards
– 1 mA to 35 mA (VCC ≤3.6 V) DESCRIPTION
– 1 mA to 45 mA (VCC > 3.6 V) The TLC59482 is a 16-channel, constant-current sink
• Global Brightness Control (BC): driver. Each channel has an individually-adjustable,
– 6-Bit (64 Steps) with 0% to 100% Range pulse width modulation (PWM) grayscale (GS)
(default is 50%) brightness control with 65,536 steps. All channels
have a 64-step global brightness control (BC). BC
• LED Power-Supply Voltage: Up to 10 V adjusts brightness deviation with other LED drivers.
• VCC: 3.0 V to 5.5 V GS and BC data are accessible via a serial interface
• Constant-Current Accuracy: port.
– Channel-to-Channel: ±1% (typ), ±2.5% (max)
– Device-to-Device: ±2% (typ), ±4% (max)
• Data Transfer Rate: 30 MHz
• Grayscale Control Clock: 33 MHz
• Auto Display Repeat
• Auto Data Refresh
• Display Timing Reset
• Four-Channel Grouped Delay Switching to
Prevent Inrush Current
• Operating Temperature: –40°C to +85°C
Typical Application Circuit (Multiple Daisy-Chained TLC59482s)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains Copyright © 2012, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
l TEXAS INSTRUMENTS
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PACKAGE ORDERING TRANSPORT MEDIA,
PRODUCT DESIGNATOR NUMBER QUANTITY
TLC59482DBQR Tape and Reel, 2500
DBQ TLC59482DBQ Tube, 50
TLC59482 TLC59482RGER Tape and Reel, 3000
RGE(2) TLC59482RGET Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Product preview device.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
MIN MAX UNIT
VCC –0.3 +6 V
SIN, SCLK, LAT, GSCLK, IREF –0.3 VCC + 0.3 V
Voltage(2) SOUT –0.3 VCC + 0.3 V
OUT0 to OUT15 –0.3 +11 V
Current IOUT (dc), OUT0 to OUT15 +55 mA
Operating junction, TJ(max) +150 °C
Temperature Storage, Tstg –55 +150 °C
Human body model (HBM) 3000 V
Electrostatic discharge (ESD)
ratings Charged device model (CDM) 2000 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to device ground terminal.
THERMAL INFORMATION
TLC59482
DBQ RGE
THERMAL METRIC(1) UNITS
(SSOP, QSOP) (QFN)
24 PINS 24 PINS
θJA Junction-to-ambient thermal resistance 86.7 35.5
θJCtop Junction-to-case (top) thermal resistance 50.4 44
θJB Junction-to-board thermal resistance 10.0 14.7 °C/W
ψJT Junction-to-top characterization parameter 13.0 0.4
ψJB Junction-to-board characterization parameter 39.7 14.8
θJCbot Junction-to-case (bottom) thermal resistance N/A 2.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
RECOMMENDED OPERATING CONDITIONS
At TA= –40°C to +85°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DC CHARACTERISTICS (VCC = 3 V to 5.5 V)
VCC Supply voltage 3.0 5.5 V
VOVoltage applied to output OUT0 to OUT15 10 V
VIH High-level input voltage SIN, SCLK, LAT, GSCLK 0.7 × VCC VCC V
VIL Low-level input voltage SIN, SCLK, LAT, GSCLK GND 0.3 × VCC V
IOH High-level output current SOUT –2 mA
IOL Low-level output current SOUT 2 mA
OUT0 to OUT15, 35 mA
3 V ≤VCC ≤3.6 V
IOLC Constant output sink current OUT0 to OUT15, 45 mA
3.6 V < VCC ≤5.5 V
TAOperating free-air temperature range –40 +85 °C
TJOperating junction temperature range –40 +125 °C
AC CHARACTERISTICS (VCC = 3 V to 5.5 V)
VCC Supply voltage 3.0 5.5 V
SCLK, 3.0 V ≤VCC ≤3.6 V 25 MHz
fCLK (SCLK) Data shift clock frequency SCLK, 3.6 V < VCC ≤5.5 V 30 MHz
fCLK (GSCLK) Grayscale control clock frequency GSCLK 33 MHz
tWH0 SCLK 10 ns
tWL0 SCLK 10 ns
tWH1 Pulse duration GSCLK 10 ns
tWL1 GSCLK 10 ns
tWH2 LAT 10 ns
tSU0 SIN to SCLK↑4 ns
tSU1 Setup time LAT↑to SCLK↑2 ns
tSU2 LAT↓to SCLK↑(1) 5 ns
tH0 SCLK↑to SIN 4 ns
tH1 SCLK↑to LAT↑7 ns
Hold time
tH2 SCLK↑to LAT↓14 ns
tH3 LAT↓to GSCLK↑30 ns
(1) Refer to the tD1 parameter in the Switching Characteristics table for the FC data read time.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: TLC59482
I at V = 0.8 V
OLC OUTn n
(I at V = 3 V) (I at V = 0.8 V)
OLC OUTn-
n n nOLC OUT
D(%/V) = ´
3 V 0.8 V-
100
I at V = 3.0 V
OLC CCn
(I at V = 5.5 V) (I at V = 3.0 V)
OLC OLC CCn n
CC -
D(%/V) = ´
5.5 V 3 V-
100
I (mA) = 39.8
OLC (IDEAL)n´1.20
RIREF ( )W
D(%) =
Ideal Output Current
-Ideal Output Current
(I + I + ... I + I )
OLC0 OLC1 OLC14 OLC15
16 ´100
D(%) =
-1
IOLCn
I + I + ... + I + I
OLC0 OLC1 OLC15OLC14
16
´100
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS
At TA= –40°C to +85°C and VCC = 3 V to 5.5 V, unless otherwise noted. Typical values are at TA= +25°C and VCC = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage (SOUT) IOH = –2 mA VCC – 0.4 VCC V
VOL Low-level output voltage (SOUT) IOL = 2 mA 0.4 V
VIREF Reference voltage output RIREF = 1.5 kΩ1.175 1.200 1.225 V
Input current
IIN VIN = VCC or GND –1 1 μA
(SIN, SCLK, GSCLK)
SIN, SCLK, LAT, GSCLK = GND, GSn= 0000h,
ICC0 1.5 3 mA
BC = 3Fh, VOUTn = 0.8 V, RIREF = open
SIN, SCLK, LAT, GSCLK = GND, GSn= 0000h,
ICC1 BC = 3Fh, VOUTn = 0.8 V, RIREF = 3 kΩ3 5 mA
(IOUTn = 15.9-mA target)
Supply current (VCC)SIN, SCLK, LAT = GND, GSCLK = 33 MHz,
ICC2 GSn= FFFFh, BC = 3Fh, VOUTn = 0.8 V, RIREF = 3 kΩ8 10 mA
(IOUT = 15.9-mA target)
SIN, SCLK, LAT = GND, GSCLK = 33 MHz,
ICC3 GSn= FFFFh, BC = 3Fh, VOUTn = 0.8 V, RIREF = 1.5 kΩ9 13.5 mA
(IOUT = 31.8-mA target)
Constant output sink current All OUTn= on, BC = 3Fh, VOUTn = VOUTfix = 0.8 V,
IOLC 29.8 31.8 33.8 mA
(OUT0 to OUT15) RIREF = 1.5 kΩ, TA= +25°C (IOLCn = 31.8-mA target)
IOLKG0 TJ= +25°C 0.1 μA
All OUTn= off, GSn= 0000h,
Output leakage current VOUTn = VOUTfix = 10 V,
IOLKG1 TJ= +85°C(1) 0.2 μA
(OUT0 to OUT15) RIREF = 1.5 kΩ
(IOLCn = 31.8-mA target)
IOLKG2 TJ= +125°C(1) 0.3 0.8 μA
Constant-current error, All OUTn= on, BC = 3Fh, VOUTn = VOUTfix = 0.8 V,
ΔIOLC0 channel-to-channel RIREF = 1.5 kΩ, TA= +25°C ±1% ±2.5%
(OUT0 to OUT15)(2) (IOUTn = 31.8-mA target)
Constant-current error, All OUTn= on, BC = 3Fh, VOUTn = VOUTfix = 0.8 V,
ΔIOLC1 device-to-device RIREF = 1.5 kΩ, TA= +25°C ±2% ±4%
(OUT0 to OUT15)(3) (IOUTn = 31.8-mA target)
VCC = 3.0 V to 5.5 V, all OUTn= on, BC = 3Fh,
Line regulation
ΔIOLC2 VOUTn = VOUTfix = 0.8 V, RIREF = 1.5 kΩ±1 ±3 %/V
(OUT0 to OUT15)(4) (IOUTn = 31.8-mA target)
All OUTn= on, BC = 3Fh, VOUTn = 0.8 V to 3.0 V,
Load regulation
ΔIOLC3 VOUTfix = 0.8 V, RIREF = 1.5 kΩ±1 ±3 %/V
(OUT0 to OUT15)(5) (IOUTn = 31.8-mA target)
RPDWN Pull-down resistor LAT 250 500 750 kΩ
(1) Not tested; specified by design.
(2) The deviation of each output from the average of OUT0 to OUT15 constant-current. Deviation is calculated by the formula:
where n = 0 to 15.
(3) The deviation of the OUTnoutput current value from the ideal constant-current value. Deviation is calculated by the formula:
Ideal current is calculated by the formula:
where n = 0 to 15.
(4) Line regulation is calculated by the formula:
where n = 0 to 15.
(5) Load regulation is calculated by the equation:
where n = 0 to 15.
4Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
SWITCHING CHARACTERISTICS
At TA= –40°C to +85°C, VCC = 3 V to 5.5 V, CL= 15 pF, RL= 110 Ω, RIREF = 1.5 kΩ, and VLED = 5.0 V, unless otherwise
noted. Typical values are at TA= +25°C and VCC = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR0 SOUT 1.5 5 ns
Rise time
tR1 OUTn, BC = 7Fh, TA= +25°C 30 ns
tF0 SOUT 1.5 5 ns
Fall time
tF1 OUTn, BC = 7Fh, TA= +25°C 30 ns
tD0 SCLK↑to SOUT↑↓ 23 35 ns
tD1 LAT↓to SOUT↑↓ 27 42 ns
GSCLK↑to OUT0, OUT7, OUT8, OUT15 on/off with
tD2 50 ns
BC = 7Fh, TA= +25°C
GSCLK↑to OUT1, OUT6, OUT9, OUT14 on/off with
Propagation delay
tD3 55 ns
BC = 7Fh, TA= +25°C
GSCLK↑to OUT2, OUT5, OUT10, OUT13 on/off with
tD4 60 ns
BC = 7Fh, TA= +25°C
GSCLK↑to OUT3, OUT4, OUT11, OUT12 on/off with
tD5 65 ns
BC = 7Fh, TA= +25°C
tOUTON – tGSCLK, GSn= 0001h, GSCLK = 20 MHz,
tON_ERR Output on-time error(1) –35 10 ns
BC = 3Fh, VCC = 3.3 V, TA= +25°C
(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR = tOUT_ON – tGSCLK. tOUT_ON is the actual on-time of the constant-
current driver. tGSCLK is the GSCLK period.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TLC59482
l TEXAS VCC INSTRUMENTS VCC i G i VCC
OUTn(1)
GND
VCC
SOUT
GND
VCC
LAT
GND
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
PIN-EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Figure 1. SIN, SCLK, and GSCLK Figure 2. LAT
Figure 3. SOUT
(1) n = 0 to 15.
Figure 4. OUT0 Through OUT15
6Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
44W
¼¼
VCC
RIREF
VOUTfix
VOUTn
OUT0VCC
OUTn(1)
OUT15GND
IREF
VCC
VCC
GND
SOUT
CL
(1)
VCC
VCC
GND
IREF OUTn(1)
RIREF
RL
CL
(2) VLED
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
TEST CIRCUITS
(1) n = 0 to 15.
(2) CLincludes measurement probe and jig capacitance.
Figure 5. Rise Time and Fall Time Test Circuit for OUTn
(1) CLincludes measurement probe and jig capacitance.
Figure 6. Rise Time and Fall Time Test Circuit for SOUT
(1) n = 0 to 15.
Figure 7. Constant-Current Test Circuit for OUTn
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: TLC59482
{9 TEXAS INSTRUMENTS _-- GND
t , t , t , t , t , t , t , t , t , t :
R0 R1 F0 F1 D0 D1 D2 D3 D4 D5
Input(1) 50%
50%
90%
10%
Output
tD
t or t
R F
V or V
OL OUTnL
V or V
OH OUTnH
GND
VCC
t , t , t :
WH0 WL0 WL1
t , t ,
WH1 WH2
Input(1)
Clock Input(1)
Data and Control
Clock(1)
t , t , t , t , t
SU0 SU1 H0 H1 :
SU2 , t , t
H2 H3
VCC
VCC
GND
VCC
GND
GND
50%
50%
50%
tWH tWL
tSU tH
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
TIMING DIAGRAMS
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 8. Input Timing
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 9. Output Timing
8Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
“£| IiacAs INSTRUMENTS $ *‘f H M “—fi U‘ 3 ‘ 1 r—w mm ‘DumN 165w A ‘ ‘ ‘ ‘ ‘ ‘ pm IE wwmfl *; 1L 14 est est ‘ um m m ‘ ‘ BA III-In.”-
tH1
tSU2
tD1
tR1
tF1
tD3
tD2
tH2
GS1
1A
1 2 --- 14 15 168 9 10 11 12 13 14 15 16
tWH0
tWL0
GS1
4A
tD0
GS1
8A
tWH2
SIN
LAT
SOUT
tSU0 tH0
t , t
R0 F0
GS1
3A
Old Data New Data (GS15-15A to GS0-0A)
SCLK
ON
OFF
ON
OFF
ON
OFF
ON
OFF
tOUTON
tOUTON
GSCLK
GS Second Data
Latch (Internal)
GS1
2A
GS1
0A
GS1
15A
GS1
14A
GS1
13A
tH3
tSU1
GS1
7A
GS1
6A
GS1
5A GS0
1A
GS0
14A
GS0
13A
GS0
0A
GS0
15A
GS2
0A
GS2
1A
GS2
2A
GS2
3A
GS2
4A
GS2
5A
GS2
6A
GS2
7A
GS1
1A
GS1
0A
GS0
15A
tWL1
tWH1
Old Data
GS Third Data
Latch (Internal)
New Data (GS15-15A to GS0-0A)
t = t t
ON_ERR OUTON -GSCLK
GS data are one case.
tD4 tOUTON
tD5 tOUTON
FC data are loaded into the common shift register
when the READFC command is input.
GS data are updated at the same time as the second
GS data when auto data refresh is disabled (XFRESH = 1).
OUT0, OUT7,
OUT8, OUT15
OUT1, OUT6,
OUT9, OUT14
OUT2, OUT5,
OUT10, OUT13
OUT3, OUT4,
OUT11, OUT12
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
(1) NV = Not valid; these data are not used for any function.
Figure 10. Timing Diagram
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: TLC59482
‘5‘ TEXAS INSTRUMENTS 333333333333 CCCCCCCCCCCC oooooooo Sow K L UUUUUU CCCCCC flflflflflfl
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
GSCLK
OUT15
OUT14
OUT13
OUT12
OUT11
1
2
3
4
5
6
18
17
16
15
14
13
Thermal Pad
(Bottom Side)
SCLK
24
OUT5 7
SIN
23
OUT6 8
GND
22
OUT7 9
VCC
21
OUT8 10
IREF
20
OUT9 11
SOUT
19
OUT10 12
GND
SIN
SCLK
LAT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VCC
IREF
SOUT
GSCLK
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
PIN CONFIGURATIONS
DBQ PACKAGE
SSOP-24, QSOP-24
(Top View)
RGE PACKAGE
QFN-24
(Top View)
NOTE: The thermal pad is not internally connected to GND. The thermal pad must be connected to GND via the printed board circuit (PCB)
pattern.
10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
PIN DESCRIPTIONS
PIN
NO.
NAME DBQ RGE I/O DESCRIPTION
GND 1 22 — Power ground
Grayscale (GS) pulse width modulation (PWM) reference clock control for OUTn.
Each GSCLK rising edge increments the GS counter for PWM control.
When the TMGRST command is input with the TMRSTEN bit (equal to '1') in the function
GSCLK 21 18 I control data latch, all constant-current outputs (OUT0 to OUT15) are forced off and the GS
counter is reset to '0'. Furthermore, all constant-current outputs are forced off and the GS
counter is reset to '0' when the LATGS command is input with the XRFRESH bit (equal to '1')
in the function control data latch.
Reference current terminal.
IREF 23 20 I/O A resistor connected between IREF to GND sets the maximum current for all constant-current
outputs.
The LAT falling edge latches the data from the 16-bit common shift register into the first GS
data latch for the OUTnthat are selected by either the GS data address down counter, global
LAT 4 1 I brightness control (BC) data latch, or function control (FC) data latch. The data latch is
selected by the number of input SCLK rising edges while LAT is high. This pin is internally
pulled down to GND with a 500-kΩ(typ) resistor.
OUT0 5 2 O
OUT1 6 3 O
OUT2 7 4 O
OUT3 8 5 O
OUT4 9 6 O
OUT5 10 7 O
OUT6 11 8 O Constant-current outputs.
OUT7 12 9 O Multiple outputs can be configured in parallel to increase the constant-current capability.
OUT8 13 10 O Different voltages can be applied to each output.
OUT9 14 11 O
OUT10 15 12 O
OUT11 16 13 O
OUT12 17 14 O
OUT13 18 15 O
OUT14 19 16 O
OUT15 20 17 O
Serial data shift clock.
Data present on SIN are shifted to the LSB of the 16-bit common shift register with the SCLK
SCLK 3 24 I rising edge. Data in the shift register are shifted towards the MSB at each SCLK rising edge.
The MSB of the common shift register appears on SOUT.
SIN 2 23 I Serial data input for the 16-bit common shift register
Serial data output of the 16-bit common shift register.
SOUT is connected to the 16-bit common shift register MSB. Data are clocked out at the
SOUT 22 19 O SCLK rising edge. Data in the function data latch can be read from SOUT during the READFC
command.
VCC 24 21 — Power-supply voltage
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS UT OUTO OUTI ou‘m Duns
16-Bit
Common
Shift Register
223
32
Reference
Current
Control
SCLK
LAT
GSCLK
IREF
GND
GS First
Data Latch
for OUT0
16-Bit PWM Timing Control
OUT0
SOUT
16-Bit
GS Counter
Constant Sink Current Driver with 6-Bit BC
4-Grouped Switching Delay
OUT1
256
16
16
LSB MSB
0 15
LSB MSB
0 255
VCC
SIN
LSB
0
LSB
255
OUT14 OUT15
Power-On
Reset
MSB
6
15 16 31 240
239
224
223
16
16
16 16
1616
16 161616
1 1 1 1
0
MSB
15
32
15 16 31 240
239
224
LAT
Command
Decoder
LAT16B
LAT256B
LATFC
Function Control (FC) Data Latch
XTMGRST
BC
XRFRESH
LATMODE
XRST
LSB
0 255
MSB
16
32
15 16 31 240
239
224
223
16 161616
LAT3RD
ADR[15:0]
XRST
Grayscale (GS)
Data Latch
Address Counter
PRIODEND
GS First
Data Latch
for OUT1
GS First
Data Latch
for OU14
GS First
Data Latch
for OUT15
GS Second
Data Latch
for OUT0
GS Second
Data Latch
for OUT1
GS Second
Data Latch
for OUT14
GS Second
Data Latch
for OUT15
GS Third
Data Latch
for OUT0
GS Third
Data Latch
for OUT1
GS Third
Data Latch
for OUT14
GS Third
Data Latch
for OUT15
XRST
216
1
SCLKB
SCLK
SCLKB
LOAD
16
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS h\\ \ \ ‘ ‘ ‘ / i ‘ ‘ / /
−3
−2
−1
0
1
2
3
−40 −20 0 20 40 60 80 100
Ambient Temperature (°C)
Constant−Current Error (%)
VCC = 5 V, BC = 3Fh, VOUTn = 0.8 V, IOLCMax = 35 mA
G004
0
10
20
30
40
50
0 8 16 24 32 40 48 56 63
IOLCMax = 45 mA
IOLCMax = 35 mA
IOLCMax = 20 mA
IOLCMax = 10 mA
IOLCMax = 1 mA
BC Data (Decimal)
Output Current (mA)
VCC = 5 V, VOUTn = 0.8 V, TA = +25°C
G005
31
32
33
34
35
36
37
38
39
0 0.5 1 1.5 2 2.5 3
Output Voltage (V)
Output Current (mA)
TA = −40°C
TA = +25°C
TA = +85°C
VCC = 5 V, BC = 3Fh, IOLCMax = 35 mA
G002
−3
−2
−1
0
1
2
3
0 10 20 30 40 50
Output Current (mA)
Constant−Current Error (%)
VCC = 5 V, BC = 3Fh, VOUTn = 0.8 V, TA = +25°C
G003
1
10
100
0 10 20 30 40 50
Output Current (mA)
Reference Resistor (kΩ)
G000
0
10
20
30
40
50
60
0 0.5 1 1.5 2 2.5 3
IOLCMax = 45 mA
IOLCMax = 35 mA
IOLCMax = 20 mA
IOLCMax = 10 mA
IOLCMax = 1 mA
Output Voltage (V)
Output Current (mA)
VCC = 5 V, BC = 3Fh, TA = +25°C
G001
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
TYPICAL CHARACTERISTICS
At TA= +25°C, unless otherwise noted.
Figure 11. REFERENCE RESISTOR Figure 12. OUTPUT CURRENT
vs OUTPUT CURRENT vs OUTPUT VOLTAGE
Figure 13. OUTPUT CURRENT Figure 14. CONSTANT-CURRENT ERROR vs
vs OUTPUT VOLTAGE OUTPUT CURRENT SET BY EXTERNAL RESISTOR
Figure 15. CONSTANT-CURRENT ERROR Figure 16. GLOBAL BRIGHTNESS
vs AMBIENT TEMPERATURE CONTROL LINEARITY
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS
0
2
4
6
8
10
12
14
16
18
20
0 10 20 30 40 50
Output Current (mA)
ICC (mA)
VCC = 5.0 V
VCC = 3.3 V
TA = +25°C, SIN = 17.5 MHz, SCLK = 25 MHz,
GSCLK = 33 MHz, All GS data = FFFFh,
BC = 3Fh, VOUTn = 0.8 V
G006
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, unless otherwise noted.
Figure 17. SUPPLY CURRENT
vs OUTPUT CURRENT
14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS Imam
63
BCn
I (mA) = (mA)
OUTnIOLCMax ´
R =
IREF (k )W
IOLCMax (mA)
VIREF (V)
´39.8
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
DETAILED DESCRIPTION
MAXIMUM CONSTANT SINK CURRENT VALUE
The maximum output current value of each channel (IOLCMax) is programmed by a single resistor (RIREF) that is
placed between the IREF and GND pins. The current value can be calculated by Equation 1:
Where:
VIREF = the internal reference voltage on IREF (typically 1.20 V when the global BC data are at maximum)
IOLCMax =1mAto35mA(3V≤VCC ≤3.6 V) or 1 mA to 45 mA (3.6 V < VCC ≤5.5 V) at OUTnand BC =
63 (1)
IOLCMax is the highest current for each output. Each output sinks IOLCMax current when it is turned on and the
global brightness control (BC) data are set to the maximum value of 3Fh (64). Each output sink current can be
reduced by lowering the BC value.
RIREF must be between 1.06 kΩand 47.8 kΩin order to hold IOLCMax between 45 mA (typ) and 1 mA (typ).
Otherwise, the output may be unstable. Output currents lower than 1 mA can be achieved by setting IOLCMax to
1 mA or higher and then using global BC to lower the output current.
Table 1 shows the characteristics of the constant-current sink versus the external resistor, RIREF.
Table 1. Maximum Constant-Current Output versus External Resistor Value
IOLC FOLLOWING POWER-UP (mA, BC =
IOLCMax (mA) RIREF (kΩ, typ)
32)
45 (VCC > 3.6 V only) 22.5 1.06
40 (VCC > 3.6 V only) 20 1.19
35 17.5 1.37
30 15 1.59
25 12.5 1.91
20 10 2.39
15 7.5 3.18
10 5 4.78
5 2.5 9.55
1 0.5 47.8
GLOBAL BRIGHTNESS CONTROL (BC) FUNCTION
The TLC59482 can simultaneously adjust the output current of all constant-current outputs. This function is
called global brightness control (BC). The global BC for all outputs (OUT0 to OUT15) is programmed with a 6-bit
word. The global BC adjusts all output currents in 64 steps from 0% to 100%, where 100% corresponds to the
maximum output current set by RIREF.Equation 2 calculates the actual output current as a function of RIREF and
global BC value. BC data can be set via the serial interface. When the device is powered on, the BC data in the
function control (FC) data latch is set to 32 as the initial value.
The output current value controlled by BC can be calculated by Equation 2.
Where:
IOLCMax = the maximum constant-current value for each output determined by RIREF
BC = the global brightness control value in the brightness control data latch (0 to 63) (2)
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
Table 2 summarizes the BC data versus the set current value.
Table 2. BC Data versus Constant-Current Ratio and Set Current Value
BC DATA RATIO OF OUTPUT IOUT (mA)
CURRENT TO (IOLCMax= 45 mA, IOUT (mA)
BINARY DECIMAL HEX IOLCMax(%) typ) (IOLCMax= 1 mA, typ)
00 0000 0 00 0 0 0
00 0001 1 01 1.6 0.71 0.02
00 0010 2 02 3.2 1.43 0.03
——————
01 1111 31 1F 49.2 22.14 0.49
10 0000 (default) 32 (default) 20 (default) 50.8 22.86 0.51
10 0001 33 21 52.4 23.57 0.52
——————
11 1101 61 3D 96.8 43.57 0.97
11 1110 62 3E 98.4 44.29 0.98
11 1111 63 3F 100.0 45.00 1.00
GRAYSCALE (GS) FUNCTION (PWM CONTROL)
The TLC59482 can adjust the brightness of each output channel using a pulse width modulation (PWM) control
scheme. The architecture of 16 bits per channel results in 65,536 brightness steps, from 0% up to 100%
brightness.
The PWM operation is controlled by the grayscale (GS) counter based on the GS data in the third GS data latch.
The GS counter increments on each rising edge of the grayscale reference clock (GSCLK). When the TMGRST
command is input with the TMRSTEN bit (equal to '1') of the function control data latch, or when the LATGS
command is input with the XRFRESH bit (equal to '1') of the function control data latch, all constant-current
outputs (OUT0 to OUT15) are forced off, the GS counter is reset to ‘0’, and the GS PWM timing controller is
initialized.
The on-time (tOUT_ON) of each output (OUTn) can be calculated by Equation 3.
tOUT_ON (ns) = tGSCLK × GSn
where:
tGSCLK is on GS clock period
GSnis the programmed GS value for OUTn(0 to 65535) (3)
16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
Table 3 summarizes the GS data values versus the output on-time duty cycle in a 16-bit length PWM. When the
device powers up, all outputs are forced off and do not turn on until the 256-bit GS data are written to the third
data latch even if GSCLK is input.
Table 3. Output Duty Cycle and On-Time versus GS Data (16-Bit PWM Bit Length)
GS DATA GS DATA
ON-TIME RATE vs ON-TIME RATE vs
DECIMAL HEX MAX GS (%) DECIMAL HEX MAX GS (%)
0 0 0 32768 8000 50.001
1 1 0.002 32769 8001 50.002
2 2 0.003 32770 8002 50.004
3 3 0.005 32771 8003 50.005
——————
8191 1FFF 12.499 40959 9FFF 62.499
8192 2000 12.500 40960 A000 62.501
8193 2001 12.502 40961 A001 62.502
——————
16383 3FFF 24.999 49151 BFFF 75.000
16384 4000 25.000 49152 C000 75.001
16385 4001 25.002 49153 C001 75.003
——————
24575 5FFF 37.499 57343 DFFF 87.500
24576 6000 37.501 57344 E000 87.501
24577 6001 37.502 57345 E001 87.503
——————
32765 7FFD 49.996 65533 FFFD 99.997
32766 7FFE 49.998 65534 FFFE 99.998
32767 7FFF 49.999 65535 FFFF 100.000
Enhanced Spectrum (ES) PWM Control
In this PWM control, the entire display period is divided into 128 display segments. The total display period is the
time from the first grayscale clock (GSCLK) to the 65,536th GS clock input for the 16-bit length PWM. Each
display segment has a maximum of 512 grayscale clocks (maximum). The OUTnon-time changes, depending on
the 16-bit grayscale data. Refer to Table 4 for the sequence of information and to Figure 18 for the timing
information.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
Table 4. ES PWM Drive Turn On-Time Length
GS DATA
DECIMAL HEX OUTnDRIVER OPERATION
0 0000h Does not turn on
1 0001h Turns on for one GSCLK period in the first display segment
2 0002h Turns on for one GSCLK period in the first and 65th display segments
3 0003h Turns on for one GSCLK period in the first, 65th, and 33th display segments
4 0004h Turns on for one GSCLK period in the first, 65th, 33th, and 97th display segments
5 0005h Turns on for one GSCLK period in the first, 65th, 33th, 97th, and 17th display segments
6 0006h Turns on for one GSCLK period in the first, 65th, 33th, 97th, 17th, and 81th display segments
The number of display segments where OUTnis turned on for one GSCLK is incremented by
increasing the GS data in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 >
101 > 21 > 85 > 53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83
— — > 51 > 115 > 11 > 75 > 43 > 107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 >
15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 > 2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42
> 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86 > 54 > 118 > 14 > 78 > 46 > 110 > 30 >
94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44 > 108 > 28 > 92 > 60 >
124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 > 128.
Turns on for one GSCLK period in the first to 127th display segments, but does not turn on in the
127 007Fh 128th display segment
128 0080h Turns on for one GSCLK period in all display segments (first to 128th)
Turns on for two GSCLK periods in the first display period and for one GSCLK period in all other
129 0081h display periods
The number of display segments where OUTnis turned on for one GSCLK is incremented by
increasing the GS data in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 >
101 > 21 > 85 > 53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83
— — > 51 > 115 > 11 > 75 > 43 > 107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 >
15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 > 2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42
> 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86 > 54 > 118 > 14 > 78 > 46 > 110 > 30 >
94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44 > 108 > 28 > 92 > 60 >
124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 > 128.
Turns on for two GSCLK periods in the first to 127th display segments and turns on one GSCLK
255 00FFh period in the 128th display segment
256 0100h Turns on for two GSCLK periods in all display segments (first to 128th)
Turns on for three GSCLK periods in the first display segments and for two GSCLK periods in all
257 0101h other display segments
The number of display segments where OUTnis turned on for one GSCLK is incremented by
increasing the GS data in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 >
101 > 21 > 85 > 53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83
— — > 51 > 115 > 11 > 75 > 43 > 107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 >
15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 > 2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42
> 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86 > 54 > 118 > 14 > 78 > 46 > 110 > 30 >
94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44 > 108 > 28 > 92 > 60 >
124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 > 128.
Turns on for 511 GSCLK periods in the first to 127th display segments, but only turns on 510
65407 FF7Fh GSCLK periods in the 128th display segment
65408 FF80h Turns on for 511 GSCLK periods in all display segments (first to 128th)
Turns on for 512 GSCLK periods in the first display period and for 511 GSCLK periods in the
65409 FF81h second to 128th display segments
— — —
Turns on for 512 GSCLK periods in the first to 63th and 65th to 127th display segments; also turns
65534 FFFEh on 511 GSCLK periods in 64th and 128th display segments
Turns on for 512 GSCLK periods in the first to 127th display segments but only turns on 511
65535 FFFFh GSCLK periods in the 128th display segment
18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS 1mm 194:5 m» 41mg aevau 0:15:
65536
65534
65535
1 2 3
128th
Period
65th
Period
96th
Period
65023 65026
65024
65025
511 513
512 514
GSCLK
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
16382 16385
16383 16386
16384 16387
49150 49153
49151 49154
49152 49155
1st Period 97th
Period
127th
Period
(Voltage Level = High) 2nd
Period
32nd
Period
64th
Period
33rd
Period
32766 32769
32767 32770
32768 32771
1st
Period
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON t = GSCLK t = GSCLK
OFF
ON
t = GSCLK 512´
OFF
OUTn
(GS Data = 0000h)
OUTn
(GS Data = 0001h)
OUTn
(GS Data = 0002h)
OUTn
(GS Data = 0003h)
OUTn
(GS Data = 0004h)
OUTn
(GS Data = 0041h)
OUTn
(GS Data = 0080h)
OUTn
(GS Data = 0081h)
OUTn
(GS Data = 0082h)
OUTn
(GS Data = FF80h)
OUTn
(GS Data = FF81h)
OUTn
(GS Data = FFFEh)
OUTn
(GS Data = FFFFh)
t =
GSCLK 511´
t =
GSCLK 511´
t = GSCLK 512´
t = GSCLK 512´
ON
¼
¼ ¼ ¼
¼¼ ¼
¼ ¼
¼
t = GSCLK 1d´
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
(Voltage Level = Low)
t = GSCLK t = GSCLK
t = GSCLK t = GSCLK
t =
GSCLK 511´t = GSCLK 511 in 2nd to 128th Period´
t = GSCLK 511 in 2nd to 128th Period´
t = GSCLK 512 in 2nd to 127th Period´
t = GSCLK 512 in 2nd to 63rd and 65th to 127th Periods,
t = GSCLK 511 in 64th Period
´
´
t = GSCLK t = GSCLK
t = GSCLK
t = GSCLK t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK 2´t = GSCLK 2´
t = GSCLK
t = GSCLKt = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK
t = GSCLK 2´t = GSCLK 1´
t = GSCLK
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
Figure 18. ES PWM Operation
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TLC59482
{L} TEXAS INSTRUMENTS 3V<5 5v="" ffffm="" (as="" dan="">
1
2
3
Written Data by 16 “WRTGS” Command
256 SCLK for 16-bit
* 16-word writing
65534 1
65535 2
65536 3
65534 1
65535 2
65536 3
Third Entire
Display Period
GS Third Data
Latch (Internal)
(GS Data = FFFFh)
GSCLK
OUT
Second Entire
Display Period
Display period is repeated
by auto display repeat
function.
OFF
ON
First Entire
Display Period
OFF OFF
LAT
SCLK
VCC 0V
3V~5.5V
First
“LATGS”
Command
SIN
16 LAT for
16
“WRTGS”
Command
2 SCLK for
“LATGS”
Command
1
2
512
OUTn is turned on
at 513th GSCLK after first
“LATGS” command is input.
Unknown
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
Auto Display Repeat Function
This function can repeat the total display period as long as GSCLK is present, as shown in Figure 19. This
function is always enabled. OUTnturn on at the 513th GSCLK after the first LATGS command is input.
Figure 19. Auto Display Repeat Function
Auto Data Refresh Function
This function allows users to input grayscale (GS) data at any time without synchronizing the input to the display
timing. When the LATGS command is input with the auto data refresh function enabled (XRFRESH bit = 0), the
256-bit data in the first GS data latch are copied only to the second GS data latch. The data in the second GS
data latch are copied to the third data latch when the 65,536th GSCLK occurs. The third latch data are used for
constant-current output (OUT0-OUT15) for the next display period.
When the LATGS command is input with the auto data refresh function disabled (XRFRESH bit = 1), the 256-bit
data in the first GS data latch are copied to the second and third GS data latches at the same time and the GS
data in the third data latch are used for OUT0-OUT15 on/off control from the next input GSCLK rising edge.
Furthermore, the GS counter is set to '0' and all constant-current outputs (OUTn) are forced off. Refer to
Figure 20 for a timing diagram of the auto data refresh function.
20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS mm} ’ X \ . A\\ \X \ , __________ as ___________________________________________ X \ ______________________________
GS1
0B
When Auto data refresh mode is enabled,
the all data in GS second data latch are copied
to GS third data latch at 65536th GSCLK.
GS15
14C
GS15
15C
GS0
1B
GS0
15B
Dotted line LAT timing
is accepted.
OUT15
GS1
0B
SIN
LAT
GS0
15B
SCLK
1
GS0
5B GS0
4B GS0
3B
Shift Register
LSB Data
(Internal)
GS1
1B
GS1
0B
Shift Register
LSB+1 Data
(Internal)
GS1
14B GS1
13B
Shift Register
MSB-1 Data
(Internal)
GS1
15B
GS1
14B
OUT1
SOUT
GS Second Data
GS Third Data
GS15
13C
GS0
2B
GS0
0B
GS0
3B
12 13 14 15 16
GS0
0B
GS0
4B
GS1
0B
New 16-bit GS Data
OUT0
Old 16-bit GS Data
Old 256-bit GS Data New 256-bit GS Data
Old 256-bit GS Data New 256-bit GS Data
The all data in 16-bit common shift
register are copied to GS0 first data
latch at falling edge of LAT.
2 or 3 rising edge of SCLK is needed
to be input while LAT is high level.
OUT0
GSCLK
- - - - 65535 1 3
65534 65536 2- - - -
GS15
12C
GS15
11C
GS15
10C
GS0
12B
GS0
14B
GS0
13B
GS0
11B
GS0
10B
GS0
9B
GS0
11B
GS0
13B
GS0
12B
GS0
10B
GS0
9B
GS0
8B
GS15
14C
GS0
0B
GS15
15C
GS15
13C
GS15
12C
GS15
11C
GS15
13C
GS15
15C
GS15
14C
GS15
12C
GS15
11C
GS15
10C
OFF
ON
The all data in GS first data
latch are copied to GS
second data latch.
GS0
2B
GS0
1B
GS0
6B
GS0
5B
GS0
4B
GS0
1B
GS0
3B
GS0
2B
GS1
3B
GS1
2B
GS1
1B GS0
14B
GS1
0B GS0
15B
GS1
4B
GS1
3B
GS1
2B
GS0
15B
GS1
1B
GS Data Latch
Address Counter
(Internal)
OUT15 GS First
Data Latch
(Internal)
OUT0 GS First
Data Latch
Latch (Internal)
OUT
(GS data = FFFFh)
Dotted line LAT
timing is accepted.
Latch (Internal)
(Internal)
The LATGS command executes.
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
Figure 20. Auto Data Refresh Function (XRFRESH = 0, LATMODE = 0)
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS UT Comm ercun
16-bit
Common
Shift Register
223
32
LOAD
GS
First Latch
for OUT0
SOUT
256
LSB MSB
0 15
LSB MSB
0 255
SIN
LSB
0
LSB
255
MSB
15 16 31 240
239
224
223
16 16
1616
16 161616
0
MSB
15
32
15 16 31 240
239
224
Function Control (FC) Data Latch
LSB
0 255
MSB
16
32
15 16 31 240
239
224
223
16 161616
GS
First Latch
for OUT1
GS
First Latch
for OU14
GS
First Latch
for OUT15
GS
Second Latch
for OUT0
GS
Second Latch
for OUT1
GS
Second Latch
for OUT14
GS
Second Latch
for OUT15
GS
Third Latch
for OUT0
GS
Third Latch
for OUT1
GS
Third Latch
for OUT14
GS
Third Latch
for OUT15
SCLK
LAT DIN
Latch Signal for GS Second
Data Latch (Internal)
To Constant Current Output/
PWM Timing Control/Data Latch
Control Circuit
To PWM Timing
Control Circuit
OUT15 GS Data Latch (Internal)
OUT14 GS Data Latch (Internal)
OUT13~2 GS Data Latch (Internal)
OUT1 GS Data Latch (Internal)
OUT0 GS Data Latch (Internal)
16
16
12
Latch Signal for GS Third
Data Latch (Internal)
Latch Signal for FC
Data Latch (Internal)
16
16
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
REGISTER AND DATA LATCH CONFIGURATION
The TLC59482 has one common shift register, one function control (FC) data latch, and a set of three data
latches: the first, second, and third grayscale (GS) data latches. The common shift register and FC data latch are
16 bits long and the GS data latches are 256 bits long. Figure 21 shows the common shift register and the data
latches configuration.
Figure 21. Shift Register and Data Latch Configuration
22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS MMC
OUT14
GS0
0A
SIN
LAT
GS15
15B
GS15
14B
GS15
13B
GS15
12B
GS15
11B
SCLK
1 2 3 4 5
GS15
15B
GS15
14B
GS15
13B
GS15
12B
Shift Register
LSB Data
(Internal)
GS0
1A
GS0
0A
GS15
15B
GS15
14B
GS15
13B
Shift Register
LSB+1 Data
(Internal)
GS0
14A GS0
13A
GS0
12A
GS0
11A
GS0
10A
Shift Register
MSB-1 Data
(Internal)
GS0
15A
GS0
14A
GS0
13A
GS0
12A
GS0
11A
OUT15
GS Data Latch
Address Counter
(Internal)
SOUT
GS Second Data
Latch (Internal)
GS Third Data
Latch (Internal)
10 11 12
GS14
15B
GS14
13B
GS15
2B
1 2 3
GS15
0B
GS15
1B
GS15
3B
GS14
14B
GS15
2B
GS15
0B
GS15
1B
GS15
3B
GS14
14B
GS15
0B
GS15
3B
GS15
2B
GS15
4B
GS14
15B
GS15
13B
GS0
0A
GS15
15B
GS0
1A
GS15
12B
GS15
14B
GS0
1A
GS0
0A
GS0
2A
GS15
13B
GS15
1B
GS15
14B
GS15
15B
13 14 15 16
GS15
5B
GS15
4B
GS15
6B
GS15
6B
GS15
5B
GS15
7B
GS0
3A
GS0
2A
GS0
4A
GS0
4A
GS0
3A
GS0
5A
GS15
5B
GS15
4B
GS15
6B
GS14
15B
GS0
0A
OUT15 GS First
Data Latch
(Internal)
Old 16-bit GS Data New 16-bit GS Data
OUT0 GS First
Data Latch
(Internal)
Dashed LAT
timing is accepted.
The data in the 16-bit common shift register are
copied to the first data latch of OUTn shown
by the GS data latch address counter.
The GS data latch address counter value is decreased by 1
for every WRTGS command input.When the counter value is
‘0’, if the command is input, then the value becomes ‘15’.
0 or 1 SCLK rising edge must
be input while LAT is high.
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
16-Bit Common Shift Register
The 16-bit common shift register is used to shift data from the SIN pin into the TLC59482. The data shifted into
the register are used for GS and FC data. The LSB of the common shift register is connected to SIN and the
MSB is connected to SOUT. On each SCLK rising edge, the data on SIN are shifted into the LSB and all 16 bits
are shifted towards the MSB. The register MSB is always connected to SOUT. When the device is powered up,
the data in the 16-bit common shift register are set to '0'.
First, Second, and Third Grayscale Data Latch
The first, second, and third grayscale (GS) data latches are each 256 bits long, and set the PWM timing for each
constant-current output. The on-time of all constant-current outputs is controlled by the data in the third GS data
latch. The 16-bit data are copied to the first GS data latch indicated by the GS data latch address counter when
the WRTGS command is input. The 256-bit GS data for OUTnin the first data latch are copied to the second GS
data latch when the LATGS command is input. The 256-bit data in the second data latch are copied to the third
GS data latch when the 65,536th GSCLK occurs with the XRFRESH bit in the FC data latch set to ‘0’. When the
XRFRESH bit is '1', the 256-bit data in the first data latch are copied to the second and third data latch at the
same time. When the device powers up, all constant-current outputs are forced off until GS data are written to
the third data latch. The GS data write sequence is shown in Figure 22 and Figure 23.
Figure 22. 16-Bit GS Data Write (WRTGS) Command
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS :X:X:X:X:X:X: IEIIII—II €3é5>C:::: .
GS15
15C
GS0
2B
GS0
4B
GS0
15B
GS0
14B
GS0
13B
OUT15
GS1
0B
SIN
LAT
GS0
15B
GS0
14B
GS0
13B
GS0
12B
GS0
11B
SCLK
1 2 3 4 5
GS0
15B
GS0
14B
GS0
13B
GS0
12B
Shift Register
LSB Data
(Internal)
GS1
1B
GS1
0A
Shift Register
LSB+1 Data
(Internal)
GS1
14B GS1
13A
GS1
12A
GS1
11A
GS1
10A
Shift Register
MSB-1 Data
(Internal)
GS1
15B
GS1
14A
GS1
13A
GS1
12A
GS1
11A
OUT1
GS Data Latch
Address Counter
(Internal)
SOUT
GS Second Data
Latch ( Internal)
GS Third Data
Latch (Internal)
10 11 12
GS15
15C
GS15
13C
GS0
2B
1 2 3
GS0
0B
GS0
1B
GS0
3B
GS15
14C
GS0
2B
GS0
0B
GS0
1B
GS0
3B
GS15
14C
GS0
0B
GS0
3B
GS0
13B
GS1
0A
GS0
15B
GS1
1A
GS0
12B
GS0
14B
GS1
1A
GS1
0A
GS1
2A
GS0
13B
GS0
1B
GS0
14B
GS0
15B
13 14 15 16
GS0
5B
GS0
4B
GS0
6B
GS0
6B
GS0
5B
GS0
7B
GS1
3A
GS1
2A
GS1
4A
GS1
4A
GS1
3A
GS1
5A
GS0
5B
GS0
4B
GS0
6B
GS15
15C
GS1
0B
OUT15 GS First
Data Latch
(Internal)
New 16-Bit GS Data
OUT0 GS First
Data Latch
(Internal)
Dashed LAT timing
is accepted.
OUT0
Old 16-Bit GS Data
Old 256-Bit GS Data New 256-Bit GS Data
Old 256-Bit GS Data New 256-Bit GS Data
When the auto data refresh mode is disabled,
all data in the first dataGS latch are copied
to both the second and third data latches.GS
All data in the first data latch are copiedGS
to the second data latch.GS
All data in the 16-bit common shift
register are copied to the first data latch.GS0
2 or 3 SCLK rising edges must
be input while LAT is high.
OUT0
Dotted line LAT
timing is accepted.
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
Figure 23. 256-Bit GS Data Latch (LATGS) Command (LATMODE = 0)
24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
Function Control (FC) Data Latch
The function control (FC) data latch is 16 bits long. This latch sets the brightness control (BC) data, auto data
refresh, enables or disables the display timing reset, and selects the data latch mode. When the device is
powered on, the data in the FC data latch are set to the default values, as shown in Table 5.
Table 5. Function Control Data Latch Bit Description
DEFAULT
BIT BIT VALUE
NUMBER NAME (Binary) DESCRIPTION
0 (LSB) to 3 N/A 0000 No applicable bit
Global brightness (BC) control bit (000000-111111).
This 6-bit data controls all output current with 64 steps between 0% and 100%
4-9 BC 100000 of the maximum current determined by a external resistor. When all bits are ‘0’,
all outputs are off. When the device is powered on, all output current are set to
approximately 50%.
Auto data refresh mode bit (0 = enabled, 1 = disabled).
If the LATGS command is input while this bit is '1', all data in the first grayscale
(GS) data latch are copied to both the second and third GS data latches. All
OUTnare forced off and the GS counter is also reset to '0'.
10 XRFRESH 0 If the LATGS command is input while this bit is '0', all data in the first GS data
latch are only copied to the second GS data latch. All data in the second GS
data latch are copied to the third GS data latch when the GS counter reaches
the maximum count value of 65,535. No OUTnare forced off and the GS
counter continues counting.
Display timing reset enable bit (0 = disabled, 1 = enabled).
If the TMGRST command is input while this bit is '1', the GS counter is reset to
11 TMRSTEN 0 '0'. When this occurs, all OUTnare forced off. When this bit is '0', even if the
TMGRST command is input, the GS counter is not reset to '0'.
12-14 N/A 000 No applicable bit
Latch mode select bit (0 = 15 WRTGS + 1 LATGS mode, 1 = 16 WRTGS + 1
LATGS mode).
When this bit is '1', The commands for all GS data writes are (16 × WRTGS + 1
LATGS). The 16th WRTGS command is required to latch the last GS input 16-
15 (MSB) LATMODE 0 bit data to the first GS data latch.
When this bit is '0', the commands for all GS data writes are (15 × WRTGS + 1
LATGS). The 16th WRTGS command is not required to latch the last GS input
16-bit data to the first GS data latch.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS Mmj;
SIN
LAT
1(1) *1 1 1 1
SCLK
1 2 3 4 5
SOUT
10 11 12
1
1 2 3 4
111
FC
14
FC
13
FC
15
13 14 15 16
1 11
Dashed LAT timing
is also accepted. 4 or 5 SCLK rising edges must
be input while LAT is high.
FC
12
16-bit FC data are loaded to the 16-bit
common shift register at the LAT signal falling edge.
Dashed LAT
timing is accepted.
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
Display Timing Reset Function
This function allows users to reset the GS counter using the TMGRST command described in Table 6. This
function is enabled when the TMRSTEN bit in the FC control data latch is ‘1’. The grayscale counter is reset to '0'
when the TMGRST command is input. All OUTnare forced off. Refer to Figure 26 for a display timing reset
functional timing diagram
Table 6. Function Commands Description
SCLK RISING
EDGES
COMMAND NAME WHILE LAT IS HIGH DESCRIPTION
The 16-bit data in the 16-bit common shift register are copied to the 16-bit GS latch in the
WRTGS 0 or 1 first latch selected by the GS data latch address counter. Refer to Figure 22 for a timing
(16-bit GS data write) diagram of this command operation.
All data in the first GS data latch are only copied to the second GS data latch when the
LATGS XRFRESH bit in the FC data latch is ‘0’, All data in the first GS data latch are copied to both
(256-bit GS data 2 or 3 the second and third GS data latches when the XRFRESH bit in the FC data latch is '1'. The
latch) GS data latch address counter is initialized to OUT15 at the same timing. Refer to Figure 23
for a timing diagram of this command operation.
The 16-bit data in the FC data latch are copied to the 16-bit shift register. The loaded data
READFC 4 or 5 can be read from SOUT synchronized with the SCLK rising edge. Refer to Figure 24 for a
(FC data read) timing diagram of this command operation.
WRTFC The 16-bit data in the 16-bit common shift register are copied to the FC data latch. Refer to
10 or 11
(FC data write) Figure 25 for a timing diagram of this command operation.
The GS counter is reset to '0' and all constant-current outputs (OUTn) are forced off when
TMGRST 12 or 13 the TMRSTEN bit in the FC data latch is ‘1’. However, the GS data in the third data latch
(display timing reset) are not updated. Refer to Figure 26 for a timing diagram of this command operation.
FCWRTEN FC writes are enabled by this command. This command must always be input before the
14 or 15
(FC write enable) FC data write occurs. Refer to Figure 25 for a timing diagram of this command operation.
Function Commands
The TLC59482 has six commands that can be input with SCLK and LAT signals: WRTGS. LATGS, READFC,
WRTFC, TMGRST, and FCWRTEN. Refer to Figure 21 to Figure 26 for detailed command input timing diagrams
for each command. Each command function is described in Table 6.
Figure 24. FC Data Read (READFC) Command Timing Diagram
26 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS MEI-(MODE: H H ‘WMWN H n": .6.
OFF
1(1)
SIN
LAT
1 1 11
SCLK
1 2 3 4 5 10 11 12
1
1 2 3
11
13 14 15 16
111
1
GSCLK
012
OUT
All OUTn are forced off at
the LAT signal falling edge.
GS counter is reset at the LAT
signal falling edge.
Dashed LAT
timing is accepted.
1
RSTENA in
FC Data Latch
(Internal)
GS Counter
(Internal)
12 or 13 rising edges are required
to be input while LAT is high.
SCLK
Dashed LAT timing
is also accepted.
OFF
ON
FC
0
SIN
LAT
*1 *1 *1 *1 *1
SCLK
1 2 3
SOUT
15 16
FC
12
*1: Don’t Care FC
11
FC
13
FC
15
1 2 3 4 5 6 7 15 16
FC
15
FC
14
Dotted line LAT timing
is accepted too.
14 or 15 rising edge of SCLK is needed
to be input while LAT is high level for
FC write enable.
The data in 16-bit common shift register are loaded to
FC data latch at LAT signal falling edge.
FC
10 FC
9FC
1
New 16-bit FC Data
16-bit FC
Data Latch
(Internal)
Old 16-bit FC Data
10 or 11 rising edge of SCLK is needed
to be input while LAT is high level for
FC write enable.
Dotted line LAT
timing is accepted.
Dotted line LAT
timing is accepted.
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
Figure 25. FC Data Write Enable (FCWRTEN) and FC Data Write (WRTFC) Command Timing Diagram
Figure 26. Display Timing Reset (TMGRST) Command Timing Diagram
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS mmmm—uacm: mmmmmm
GS0
15A
OUT14
GS13
15A
GS1
15A
GS2
1A
GS15
15A
Dashed LAT timing is also accepted.
GS1
14A
GS14
15A
GS15
0A
GS0
14
OUT1
SIN
LAT
GS15
15A
GS15
14A
GS15
1A
SCLK
GS0
15 GS0
1GS0
0
GS Data Latch
Address Counter
(Internal)
SOUT
GS Second
Data Latch
(Internal)
GS Third
Data Latch
(Internal)
241 253 254 255 256
225 226 239 240
GS15
1A GS15
0A
OUT15 GS First
Data Latch
(Internal)
New 16-bit
GS data
OUT1 GS First
Data Latch
(Internal)
OUT15
Old 16-bit GS data
Old 256-bit
GS data
The all data in GS first data latch are copied
to both GS second and third data latch
when Auto data refresh mode is disabled.
The all data in GS first data latch
are copied to GS second data latch.
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 15’th “WRTGS” command
GS0
0
GS14
0A
GS14
1A
GS14
14A
GS1
0A
GS1
1A
GS0
0A
GS0
1A
GS0
15A
GS15
14A GS14
15A GS2
0A
GS2
14A GS1
1A
1 2 15 16 17 18 31 32
GS1
15A GS1
0A
OUT13
OUT0
OUT15
OUT14 GS First
Data Latch
(Internal)
OUT0 GS First
Data Latch
(Internal)
Old 16-bit
GS data
Old 16-bit GS data
New 16bit GS data
New 16-bit GS data
Old 16-bit GS data
The counter is set to OUT15 when
“LATGS” command is input.
The counter is decreased when
“WRTGS” command is input.
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 16’th “LATGS” command.
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 1’st “WRTGS” command
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 2’nd “WRTGS” command.
OUT15 OUT14 OUT1 OUT0
LATMODE Bit
in FC Data Latch
(Internal) 0
16-Bit Common
Shift Register
(Internal)
1st WRTGS
Command
2nd WRTGS
Command
15th WRTGS
Command
LATGS
Command
GS0
2A
GS0
3A
GS1
2A
New 16-bit
GS Data
New 256-bit
GS Data
TLC59482
SBVS218 –DECEMBER 2012
www.ti.com
Figure 27. 256-Bit GS Data Write Sequence Timing Diagram
(15 × WRTGS + 1 LATGS, LATMODE = 0)
28 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: TLC59482
l TEXAS INSTRUMENTS mwmmmm
The all data in 16-bit common shift
register are copied to GS1 first data
latch at 1’st “WRTGS” command
GS15
14A
GS0
0
GS0
0A
OUT14
GS13
15A
GS0
3A
GS1
1A
GS15
15A
Dotted line LAT timing is also accepted.
GS14
15A
GS15
0A
GS0
14
SIN
LAT
GS15
15A
GS15
1A
SCLK
GS0
15 GS0
1
GS Data Latch
Address Counter
(Internal)
SOUT
GS Second
Data Latch
(Internal)
GS Third
Data Latch
(Internal)
257 269 270 271 272
253 254 255 256
GS15
1A
GS15
0A
OUT15 GS First
Data Latch
(Internal)
OUT15
Old 256-bitGS Data
New 256-Bit
GS Data
All data in the GS data latch are copiedfirst to both the second and
third data latchesGS when the auto data refresh mode is disabled.
.
The all data in GS first data latch
are copied to GS second data latch.
GS0
0GS14
0A
GS14
1A
GS0
0A
GS0
1A
GS14
15A
GS1
0A
GS1
14A
GS0
2A
GS1
14A
1 15 16 17 31 32
GS0
15A GS0
1A
OUT13
OUT15
OUT15 GS First
Data Latch
(Internal)
New 16-Bit GS Data
OUT0 GS First
Data Latch
(Internal)
Old GS Data16-Bit
Old 16-bit GS Data New 16-Bit GS Data
New GS Data16-Bit
Old GS Data16-Bit
The counter is set to OUT15 when
the command is input.LATGS
The counter is decreased when
the WRTGS command is input.
All data in the16-bit common shift
register are copied to the GS0 datafirst
latch at the 16th WRTGS command.
All data in the 16-bit common shift
register are copied to the GS1 datafirst
latch at the 2nd WRTGS command.
OUT15 OUT14 OUT0 OUT15
LATMODE Bit
in FC Data Latch
(Internal) 1
16-Bit Common
Shift Register
(Internal)
1st WRTGS
Command
2nd WRTGS
Command
16th WRTGS
Command LATGS
Command
GS0
2A
GS0
3A
1(1) 111 1
Old 256-Bit GS Data
TLC59482
www.ti.com
SBVS218 –DECEMBER 2012
Figure 28. 256-Bit GS Data Write Sequence Timing Diagram
(16 × WRTGS + 1 LATGS, LATMODE = 1)
NOISE REDUCTION
Large surge currents may flow through the device and the board on which the device is mounted if all 16 outputs
turn on or off simultaneously. These large current surges can introduce detrimental noise and electromagnetic
interference (EMI) into other circuits.
The TLC59482 turns the outputs on with a series delay for each group independently to provide a soft-start
feature. The output current sinks are grouped into four groups. The first output group that is turned on/off are
OUT0, OUT7, OUT8, and OUT15; the second output group is OUT1, OUT6, OUT9, and OUT14; the third output
group is OUT2, OUT5, OUT10, and OUT13; and the fourth output group is OUT3, OUT4, OUT11, and OUT12.
Each output group is turned on and off sequentially with a 5-ns (typical) delay between the groups. However,
each output on/off is controlled by the GS clock.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TLC59482
I TEXAS INSTRUMENTS Sample: Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLC59482DBQ ACTIVE SSOP DBQ 24 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC59482
TLC59482DBQR ACTIVE SSOP DBQ 24 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC59482
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
I TEXAS INSTRUMENTS ‘3‘ V.'
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0 W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1 Q1Q2 Q2
Q3 Q3Q4 Q4 User Direction of Feed
P1
Reel
Diameter
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC59482DBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC59482DBQR SSOP DBQ 24 2500 356.0 356.0 35.0
Pack Materials-Page 2
I TEXAS INSTRUMENTS __________________ ‘(I(I“""""""""
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jun-2022
TUBE
L - Tube length
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TLC59482DBQ DBQ SSOP 24 50 506.6 8 3940 4.32
Pack Materials-Page 3
MECHANICAL DATA D31; U (324) ‘LASHC S‘WALL70L1LN¥ \JACXML 4 _ > HHHHHWHHHHHH ,,<, ,,,,,="" \\="" v="" ‘hmhhhmhhhhh="" ~="" 4073301="" *4/h="" 10/2008="" ah="" hnec'="" dimensmrs="" c'e="" m="" mc'ves="" ['m‘hmeters)="" th5="" drawer="" ‘5="" sumac:="" :0="" change="" mm:="" home,="" body="" dwmcnswons="" do="" not="" mcmae="" mom="" flash="" or="" cromsm="" m="" m="" exceed="" 0006="" (055)="" per="" 3m="" fuhs="" mm="" jedec="" m07137="" vunumn="" ae,="" no’es:="" cnm=""> Q; ”Dams INSI'RUMENTS www.1i.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated