Rochester Electronics, LLC 的 TMS320C28341-46 Manual 規格書

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TMS320C2834x Delfino Microcontrollers
1 Features
High-Performance Static CMOS Technology
Up to 300 MHz (3.33-ns Cycle Time)
1.1-V/1.2-V Core, 3.3-V I/O, 1.8-V PLL/
Oscillator Design
High-Performance 32-Bit CPU (TMS320C28x)
IEEE 754 Single-Precision Floating-Point Unit
(FPU)
16 × 16 and 32 × 32 MAC Operations
16 × 16 Dual MAC
Harvard Bus Architecture
Fast Interrupt Response and Processing
Code-Efficient (in C/C++ and Assembly)
Six-Channel DMA Controller (for McBSP, XINTF,
and SARAM)
16-Bit or 32-Bit External Interface (XINTF)
More Than 2M × 16 Address Reach
On-Chip Memory
Up to 258K × 16 SARAM
8K × 16 Boot ROM
Clock and System Control
On-Chip Oscillator
Watchdog Timer Module
Peripheral Interrupt Expansion (PIE) Block That
Supports All 64 Peripheral Interrupts
Endianness: Little Endian
Enhanced Control Peripherals
Eighteen Enhanced Pulse Width Modulator
(ePWM) Outputs
Dedicated 16-Bit Time-Based Counter With
Period and Frequency Control
Single-Edge, Dual-Edge Symmetric, or
Dual-Edge Asymmetric Outputs
Dead-Band Generation
PWM Chopping by High-Frequency Carrier
Trip Zone Input
Up to 9 HRPWM Outputs With 55-ps MEP
Resolution at VDD = 1.1 V (65 ps at 1.2 V)
Six 32-Bit Enhanced Capture (eCAP) Modules
Configurable as 3 Capture Inputs or
3 Auxiliary Pulse Width Modulator Outputs
Single-Shot Capture of up to Four Event
Timestamps
Three 32-Bit Quadrature Encoder Pulse (QEP)
Modules
Six 32-Bit Timers and Nine 16-Bit Timers
Three 32-Bit CPU Timers
Serial Port Peripherals
Up to 2 CAN Modules
Up to 3 SCI (UART) Modules
Up to 2 McBSP Modules (Configurable as SPI)
Up to 2 SPI Modules
One Inter-Integrated Circuit (I2C) Bus
External ADC Interface
Up to 88 Individually Programmable, Multiplexed
GPIO Pins With Input Filtering
Advanced Emulation Features
Analysis and Breakpoint Functions
Real-Time Debug Using Hardware
Package Options:
256-Ball Plastic Ball Grid Array (BGA) (ZFE)
179-Ball MicroStar BGA (ZHH)
Temperature Options:
T: –40°C to 105°C (ZFE, ZHH)
S: –40°C to 125°C (ZFE)
Q: –40°C to 125°C (ZFE)
(AEC Q100 Qualification for Automotive
Applications)
2 Applications
Industrial AC Inverter Drives
Industrial Servo Amplifiers and Controllers
Computer Numerical Control (CNC) Machining
Uninterruptible and Server Power Supplies
Telecom Equipment Power
Solar Inverters
3 Description
The TMS320C2834x (C2834x) Delfino microcontroller unit (MCU) devices build on TI's existing F2833x high-
performance floating-point microcontrollers. The C2834x delivers up to 300 MHz of floating-point performance,
and has up to 516KB of on-chip RAM. Designed for real-time control applications, the C2834x is based on the
C28x core, making it code-compatible with all C28x microcontrollers. The on-chip peripherals and low-latency
core make the C2834x an excellent solution for performance-hungry real-time control applications.
www.ti.com
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F MARCH 2009 REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 1
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
I TEXAS INSTRUMENTS
The TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, and
TMS320C28341 devices, members of the Delfino MCU generation, are highly integrated, high-performance
solutions for demanding control applications.
Throughout this document, the devices are abbreviated as C28346, C28345, C28344, C28343, C28342, and
C28341, respectively. Device Comparison provides a summary of features for each device.
Device Information (1)
PART NUMBER PACKAGE BODY SIZE
TMS320C28346ZFE BGA (256) 17.0 mm × 17.0 mm
TMS320C28345ZFE BGA (256) 17.0 mm × 17.0 mm
TMS320C28344ZFE BGA (256) 17.0 mm × 17.0 mm
TMS320C28343ZFE BGA (256) 17.0 mm × 17.0 mm
TMS320C28342ZFE BGA (256) 17.0 mm × 17.0 mm
TMS320C28341ZFE BGA (256) 17.0 mm × 17.0 mm
TMS320C28346ZEP BGA (256) 17.0 mm × 17.0 mm
TMS320C28345ZEP BGA (256) 17.0 mm × 17.0 mm
TMS320C28344ZEP BGA (256) 17.0 mm × 17.0 mm
TMS320C28343ZEP BGA (256) 17.0 mm × 17.0 mm
TMS320C28342ZEP BGA (256) 17.0 mm × 17.0 mm
TMS320C28341ZEP BGA (256) 17.0 mm × 17.0 mm
TMS320C28345ZHH BGA MicroStar (179) 12.0 mm × 12.0 mm
TMS320C28343ZHH BGA MicroStar (179) 12.0 mm × 12.0 mm
TMS320C28341ZHH BGA MicroStar (179) 12.0 mm × 12.0 mm
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
I TEXAS INSTRUMENTS E: S E E SPISIMOx SPISOMIx
3.1 Functional Block Diagram
L0 SARAM 8K x 16
(0-Wait)
L1 SARAM 8K x 16
(0-Wait)
L2 SARAM 8K x 16
(0-Wait)
L3 SARAM 8K x 16
(0-Wait)
L4 SARAM 8K x 16
(0-Wait)
L5 SARAM 8K x 16
(0-Wait)
Boot ROM
8K x 16
DMA Bus
XINTF
XWE0
XZCS6
XZCS7
XZCS0
XR/W
XREADY
XHOLD
XHOLDA
XD31:0
XA19:1
GPIO
MUX
Memory Bus
Memory Bus
XCLKOUT
XRD
GPIO
MUX
88 GPIOs 8 External Interrupts
88 GPIOs
ADC
SoC
EXTADCCLK
EXTSOC
CPU Timer 0
CPU Timer 1
CPU Timer 2
OSC,
PLL,
LPM,
WD
DMA
6 Ch
PIE
(Interrupts)
32-Bit CPU
(300 MHz @ 1.2 V
200 MHz @ 1.1 V)
EMU1
EMU0
TRST
TDO
TMS
TDI
TCK
XRS
X2
X1
XCLKIN
FPU
DMA Bus
Memory Bus
FIFO
(16 Levels)
SCI-A/B/C
FIFO
(16 Levels)
SPI-A/D
FIFO
(16 Levels)
I2C
16-Bit Peripheral Bus
SPISOMIx
SPISIMOx
SPICLKx
SPISTEx
SCIRXDx
SCITXDx
SDAx
SCLx
McBSP-A/B
MRXx
MDXx
MCLKXx
MCLKRx
MFSXx
MFSRx
32-Bit Peripheral Bus
(DMA accessible)
ePWM-1/../9
HRPWM-1/../9
eCAP-1/../6 eQEP-1/2/3
EPWMxA
EPWMxB
ESYNCI
ESYNCO
TZx
ECAPx
EQEPxA
EQEPxB
EQEPxI
EQEPxS
CAN-A/B
(32-mbox)
CANRXx
CANTXx
M0 SARAM 1K x 16
(0-Wait)
M1 SARAM 1K x 16
(0-Wait)
Memory Bus
32-Bit Peripheral Bus
GPIO MUX
88 GPIOs
XWE1
H0 SARAM 32K x 16
(1 Wait, Prefetch)
H1 SARAM 32K x 16
(1 Wait, Prefetch)
H2 SARAM 32K x 16
(1 Wait, Prefetch)
H3 SARAM 32K x 16
(1 Wait, Prefetch)
H4 SARAM 32K x 16
(1 Wait, Prefetch)
H5 SARAM 32K x 16
(1 Wait, Prefetch)
L6 SARAM 8K x 16
(1-Wait)
L7 SARAM 8K x 16
(1-Wait)
DMA Bus
Figure 3-1. Functional Block Diagram
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
3.1 Functional Block Diagram........................................... 3
4 Revision History.............................................................. 5
5 Device Comparison......................................................... 6
5.1 Related Products........................................................ 6
6 Terminal Configuration and Functions..........................8
6.1 Pin Diagrams.............................................................. 8
6.2 Signal Descriptions................................................... 16
7 Specifications................................................................ 29
7.1 Absolute Maximum Ratings (1) (2) .............................29
7.2 ESD Ratings – Automotive....................................... 29
7.3 ESD Ratings – Commercial...................................... 29
7.4 Recommended Operating Conditions.......................30
7.5 Power Consumption Summary................................. 31
7.6 Electrical Characteristics...........................................34
7.7 Thermal Resistance Characteristics......................... 35
7.8 Thermal Design Considerations................................36
7.9 Timing and Switching Characteristics....................... 37
8 Detailed Description......................................................86
8.1 Brief Descriptions......................................................86
8.2 Peripherals................................................................92
8.3 Memory Maps......................................................... 130
8.4 Register Map...........................................................136
8.5 Interrupts.................................................................139
8.6 System Control....................................................... 144
8.7 Low-Power Modes Block........................................ 151
9 Applications, Implementation, and Layout............... 152
9.1 TI Design or Reference Design...............................152
10 Device and Documentation Support........................153
10.1 Getting Started......................................................153
10.2 Device and Development Support Tool
Nomenclature............................................................ 153
10.3 Tools and Software............................................... 155
10.4 Documentation Support........................................ 156
10.5 Support Resources............................................... 158
10.6 Trademarks...........................................................158
10.7 Electrostatic Discharge Caution............................158
10.8 Glossary................................................................159
11 Mechanical, Packaging, and Orderable
Information.................................................................. 160
11.1 Packaging Information.......................................... 160
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
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4 Revision History
Changes from August 22, 2018 to February 1, 2021 (from Revision E (August 2018) to Revision
F (February 2021)) Page
Added Q1 Part Numbers................................................................................................................................ 0
Table 5-1: Added Q1 Part Numbers....................................................................................................................6
Section 7.9.4.5.1.1 (SPI Master Mode External Timing (Clock Phase = 0)): Updated MIN value (for both BRR
EVEN and BRR ODD) for Parameter 23, td(SPC)M............................................................................................ 56
Section 7.9.4.5.1.2 (SPI Master Mode External Timing (Clock Phase = 1)): Updated MIN value (for both BRR
EVEN and BRR ODD) for Parameter 23, td(SPC)M............................................................................................ 58
Figure 10-1: Added GPN information............................................................................................................. 153
www.ti.com
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TEXAS INSTRUMENTS
5 Device Comparison
Table 5-1. Device Comparison
FEATURE TYPE(1)
C28346
C28346-Q1
(300 MHz)
C28345
(200 MHz)
C28344
(300 MHz)
C28343
C28343-Q1
(200 MHz)
C28342
(300 MHz)
C28341
(200 MHz)
Package type 256-ball ZFE
BGA(2)
256-ball ZFE
BGA(2)
179-ball ZHH
BGA
256-ball ZFE
BGA(2)
256-ball ZFE
BGA(2)
179-ball ZHH
BGA
256-ball ZFE
BGA(2)
256-ball ZFE
BGA(2)
179-ball ZHH
BGA
Instruction cycle 3.33 ns 5 ns 3.33 ns 5 ns 3.33 ns 5 ns
Floating-point unit Yes Yes Yes Yes Yes Yes
Single-access RAM (SARAM)
(16-bit word) – 258K 258K 130K 130K 98K 98K
Code security for on-chip SARAM
blocks No No No No No No
Boot ROM (8K ×16) Yes Yes Yes Yes Yes Yes
16-/32-bit External Interface
(XINTF) 1 Yes Yes Yes Yes Yes Yes
6-channel Direct Memory Access
(DMA) 0 Yes Yes Yes Yes Yes Yes
PWM channels 0 ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6
ePWM1/2/3/
4/5/6
HRPWM channels 0
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A
ePWM1A/2A/
3A/4A/5A/6A
32-bit capture inputs or auxiliary
PWM outputs 0 6 6 6 6 4 4
32-bit QEP channels (four inputs/
channel) 0 3 3 3 3 2 2
Watchdog timer Yes Yes Yes Yes Yes Yes
External ADC interface Yes Yes Yes Yes Yes Yes
32-bit CPU timers 3 3 3 3 3 3
Multichannel Buffered Serial Port
(McBSP)/SPI 1 2 2 2 2 1 1
Serial Peripheral Interface (SPI) 0 2 2 2 2 2 2
Serial Communications Interface
(SCI) 0 3 3 3 3 3 3
Enhanced Controller Area
Network (eCAN) 0 2 2 2 2 2 2
Inter-Integrated Circuit (I2C) 0 1 1 1 1 1 1
General-Purpose Input/Output
(GPIO) pins (shared) 88 88 88 88 88 88
External interrupts 8 8 8 8 8 8
Temperature
options
T: –40°C to
105°C ZFE ZFE ZHH ZFE ZFE ZHH ZFE ZFE ZHH
S: –40°C to
125°C ZFE ZFE ZFE ZFE ZFE ZFE
Q: –40°C to
125°C
(AEC Q100
qualification)
ZFE ZFE ZFE ZFE ZFE ZFE
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.
(2) TMX samples will come with the ZEP designator. The designator will change to ZFE after TMS.
5.1 Related Products
For information about other devices in the Delfino family of products, see the following links:
Original Delfino™ series:
TMS320F2833x Delfino™ Microcontrollers
The F2833x series is the original Delfino MCU. It is the first C2000 MCU that is offered with a floating-point unit
(FPU). It has the first-generation ePWM timers that are used throughout the rest of the Delfino and Piccolo
families. The 12.5-MSPS, 12-bit ADC is still class-leading for an integrated analog-to-digital converter. The
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
I TEXAS INSTRUMENTS
F2833x has a 150-MHz CPU and up to 512KB of on-chip Flash. It is available in a 176-pin QFP or 179-ball BGA
package.
TMS320C2834x Delfino™ Microcontrollers
The C2834x series removes the on-chip Flash memory and integrated ADC to enable the fastest available clock
speeds of up to 300 MHz. It is available in a 179-ball BGA or 256-ball BGA package.
Newest Delfino™ series:
TMS320F2837xD Delfino™ Microcontrollers
The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a
C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are
TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta
filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The
F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package.
TMS320F2837xS Delfino™ Microcontrollers
The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA
subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the Piccolo™
TMS320F2807x series.
www.ti.com
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
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6 Terminal Configuration and Functions
6.1 Pin Diagrams
The 179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 6-1 through Figure 6-4. The
256-ball ZFE plastic BGA terminal assignments are shown in Figure 6-5 through Figure 6-8. Table 6-1 describes
the function(s) of each pin.
EXTSOC3B
GPIO19/
/
SCIRXDB/
CANTXA
SPISTEA
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO24/
ECAP1/
EQEP2A/
MDXB
EXTSOC1A
EXTSOC2A EXTSOC1B
GPIO21/
EQEP1B/
MDRA/
CANRXB
GPIO20/
EQEP1A/
MDXA/
CANTXB
P P
N N
M M
L L
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
TDI
GPIO16/
SPISIMOA/
CANTXB/
TZ5
GPIO12/
/
CANTXB/
MDXB
TZ1
EXTSOC3A
K K
J J
H H
1 2 3 4 5
6 7
TDO
VSS
1 2 345 6 7
EXTSOC2B
TRST
GPIO17/
SPISOMIA/
CANRXB/
TZ6
GPIO13/
/
CANRXB/
MDRB
TZ2
GPIO15/
/ /
SCIRXDB/
MFSXB
TZ4XHOLDA
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
EXTADCCLK
VDD
VSS
VSS
VDDIO
VDDIO
VSS
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
VDD
VDD
VDD
VSS
VDDIO
GPIO14/
/ /
SCITXDB/
MCLKXB
TZ3XHOLD
VDD
VDD
VSS
VDDIO
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
GPIO33/
SCLA/
EPWMSYNCO/
ADCSOCBO
GPIO32/
SDAA/
EPWMSYNCI/
ADCSOCAO
Figure 6-1. C2834x 179-Ball ZHH MicroStar BGA Upper-Left Quadrant (Bottom VIew)
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021 www.ti.com
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
I TEXAS INSTRUMENTS
GPIO49/
ECAP6/
XD30/
SPISOMID
VDDIO
GPIO54/
SPISIMOA/
XD25/
EQEP3A
GPIO59/
MFSRA/
XD20/
EPWM7B
GPIO55/
SPISOMIA/
XD24/
EQEP3B
GPIO60/
MCLKRB/
XD19/
EPWM8A
VSS
EMU1
GPIO /
MFSRB/
XD18/
EPWM8B
61
GPIO70/
XD9
TCK
VDD
EMU0
8 9
10 11 12 13 14
PP
NN
MM
LL
KK
JJ
HH
GPIO63/
SCITXDC/
XD16/
EPWM9B
GPIO68/
XD11
VSS
XRSIO
GPIO65/
XD14
VSS
8 9 10 11 12 13 14
XRS
VSS
TMS
VDD
GPIO67/
XD12
GPIO66/
XD13
GPIO62/
SCIRXDC/
XD17/
EPWM9A
VDD
GPIO57/
/
XD22/
EQEP3I
SPISTEA
GPIO50/
EQEP1A/
XD29/
SPICLKD
GPIO51/
EQEP1B/
XD28/
SPISTED
VSS
VDDIO VDD VSS VDD
GPIO64/
XD15
GPIO48/
ECAP5/
XD31/
SPISIMOD
GPIO52/
EQEP1S/
XD27
GPIO53/
EQEP1I/
XD26
GPIO56/
SPICLKA/
XD23/
EQEP3S
GPIO58/
MCLKRA/
XD21/
EPWM7A
VDDIO
VDDIO
VDD
GPIO69/
XD10
Figure 6-2. C2834x 179-Ball ZHH MicroStar BGA Upper-Right Quadrant (Bottom View)
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
I TEXAS INSTRUMENTS
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
GPIO10/
EPWM6A/
CANRXB/
ADCSOCBO
GPIO8/
EPWM5A/
CANTXB/
ADCSOCAO
VSS
GPIO80/
XA8
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
VDD
GPIO4/
EPWM3A
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO3/
EPWM2B/
ECAP5/
MCLKRB
GPIO46/
XA6
VDD
VSS
VDDIO
GPIO85/
XA13
GPIO84/
XA12
G
F
E
D
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO30/
CANRXA/
XA18
GPIO29/
SCITXDA/
XA19
VDD GPIO81/
XA9
GPIO0/
EPWM1A
GPIO31/
CANTXA/
XA17
GPIO87/
XA15
VDDIO GPIO83/
XA11
GPIO39/
XA16
GPIO86/
XA14 VSS
C
B
A
1 2 3 4 5 6 7
G
F
E
D
C
B
A
VDD18
VDD
VDDIO VDD
VSS
VSS
GPIO82/
XA10
1 2 3 4 5
6 7
VSS
VDD
VDDIO
GPIO6/
EPWM4A/
EPWMSYNCI/
EPWMSYNCO
GPIO2/
EPWM2A
VDD
GPIO47/
XA7 VDDIO
Figure 6-3. C2834x 179-Ball ZHH MicroStar BGA Lower-Left Quadrant (Bottom View)
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021 www.ti.com
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
I TEXAS INSTRUMENTS
GPIO71/
XD8
GPIO72/
XD7
GPIO73/
XD6
GPIO35/
SCITXDA/
XR/W
GPIO34/
ECAP1
XREADY
GPIO75/
XD4
GPIO77/
XD2
VSS
XCLKIN GPIO41/
XA1
GPIO38/
XWE0
G
F
E
D
X1
GPIO36/
SCIRXDA/
XZCS0
GPIO40/
XA0
GPIO44/
XA4
GPIO78/
XD1
C
B
A
8 9 10 11 12 13 14
G
F
E
D
C
B
A
XCLKOUT
XRD
X2
VSS
VDDIO
8 9
10 11 12 13 14
VDD18
VDD
GPIO79/
XD0
VDD
VSS
VSSK
VDDIO
GPIO45/
XA5
GPIO42/
XA2
GPIO43/
XA3
VDD
GPIO28/
SCIRXDA/
XZCS6
GPIO74/
XD5
XWE1
VSS
GPIO76/
XD3
VSS
VDD
VSS
VDDIO
GPIO37/
ECAP2/
XZCS7
VDD
VSS
VDDIO
Figure 6-4. C2834x 179-Ball ZHH MicroStar BGA Lower-Right Quadrant (Bottom View)
www.ti.com
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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” TEXAS INSTRUMENTS
VSS
1
TVSS
2
RVSS
VDDIO
PVDD
3 4 5 6 7 8
VSS
VSS
N
VSS
VDDIO VDDIO VSS
M
VDDIO
VSS
VDD
VDD
VDD
L
VDDIO
VDD
VSS VSS VSS
KVSS VDD
VSS VSS VSS VSS
JVDDIO VDD VSS VSS VSS
GPIO19/
/
SCIRXDB/
CANTXA
SPISTEA
GPIO33/
SCLA/
EPWMSYNCO/
ADCSOCBO
GPIO21/
EQEP1B/
MDRA/
CANRXB
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
GPIO20/
EQEP1A/
MDXA/
CANTXB
GPIO32/
SDAA/
EPWMSYNCI/
ADCSOCAO
GPIO27/
ECAP4/
EQEP2S/
MFSXB
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO24/
ECAP1/
EQEP2A/
MDXB
TDI
EXTSOC3A
EXTADCCLK
EXTSOC2B
TRST
EXTSOC3B
EXTSOC2A
TDO
GPIO17/
SPISOMIA/
CANRXB/
TZ6
GPIO15/
/ /
SCIRXDB/
MFSXB
TZ4XHOLDA
VDDIO
GPIO14/
/ /
SCITXDB/
MCLKXB
TZ3XHOLD
GPIO13/
/
CANRXB/
MDRB
TZ2
GPIO16/
SPISIMOA/
CANTXB/
TZ5
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
EXTSOC1A EXTSOC1B VDD
VDDIO VSS VDD
Figure 6-5. C2834x 256-Ball ZFE Plastic BGA Upper-Left Quadrant (Bottom View)
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021 www.ti.com
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
Q TEXAS INSTRUMENTS
VDDIO
9
T
VSS
10
R
P
11 12
GPIO58/
MCLKRA/
XD21/
EPWM7A
13 14 15 16
GPIO64/
XD15
GPIO59/
MFSRA/
XD20/
EPWM7B
GPIO57/
/
XD22/
EQEP3I
SPISTEA
GPIO56/
SPICLKA/
XD23/
EQEP3S
N
VSS VSS
VDDIO VDDIO
M
VSS
L
VDD VDDIO
TCK
K
VSS
J
GPIO63/
SCITXDC/
XD16/
EPWM9B
GPIO60/
MCLKRB/
XD19/
EPWM8A
VDD
VSS
VSS
GPIO68/
XD11
GPIO66/
XD13
GPIO61/
MFSRB/
XD18/
EPWM8B
VSS VSS
GPIO65/
XD14
GPIO69/
XD10
GPIO67/
XD12
GPIO62/
SCIRXDC/
XD17/
EPWM9A
VDDIO
VSS
VSS
VDDIO
GPIO53/
EQEP1I/
XD26
GPIO55/
SPISOMIA/
XD24/
EQEP3B
GPIO54/
SPISIMOA/
XD25/
EQEP3A
VDD VDD VDD VDDIO
GPIO50/
EQEP1A/
XD29/
SPICLKD
GPIO52/
EQEP1S/
XD27
GPIO51/
EQEP1B/
XD28/
SPISTED
VSS VSS VSS
GPIO49/
ECAP6/
XD30/
SPISOMID
GPIO48/
ECAP5/
XD31/
SPISIMOD
VSS VSS VDD VSS
XRS
EMU0
EMU1
VSS VSS VSS VDD
VSS
TMS
VDDIO
XRSIO
Figure 6-6. C2834x 256-Ball ZFE Plastic BGA Upper-Right Quadrant (Bottom View)
www.ti.com
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
” TEXAS INSTRUMENTS
VSSK
1
H
2
X1
G
VDD18
F
3 4 5 6 7 8
GPIO81/
XA9
GPIO82/
XA10
E
GPIO84/
XA12
GPIO85/
XA13
D
GPIO39/
XA16
C
VDDIO
GPIO31/
CANTXA/
XA17
BVSS
GPIO30/
CANRXA/
XA18
A
VDD
GPIO46/
XA6
GPIO47/
XA7
VDDIO
VDD VSS VSS VSS
GPIO80/
XA8
VSS
VDD
VSS VSS VSS
GPIO83/
XA11
VDDIO
VDD
VSS VSS VSS
GPIO86/
XA14
VDDIO VSS VDD VDD
VDD
GPIO87/
XA15
VSS VSS VDDIO VDDIO VSS
VSS
VSS VSS
GPIO6/
EPWM4A/
EPWMSYNCI/
EPWMSYNCO
GPIO3/
EPWM2B/
ECAP5/
MCLKRB
GPIO12/
/
CANTXB/
MDXB
TZ1
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
VSS
GPIO0/
EPWM1A
GPIO2/
EPWM2A
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO8/
EPWM5A/
CANTXB/
ADCSOCAO
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
VSS VSS
GPIO29/
SCITXDA/
XA19
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO4/
EPWM3A
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO10/
EPWM6A/
CANRXB/
ADCSOCBO
Figure 6-7. C2834x 256-Ball ZFE Plastic BGA Lower-Left Quadrant (Bottom View)
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021 www.ti.com
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
Q TEXAS INSTRUMENTS
9
H
VSS
10
G
F
11 12 13 14 15 16
E
C
B
A
D
VSS
VSS VSS VDD
VSS
VSS
VSS VDD VSS
VSS
VSS
VSS VDD VDDIO
VDD VDD VDD VSS VDDIO
VDD18
VSS VDDIO VDDIO VSS VSS
VDD
VSS
VDDIO
VSS VSS
VDDIO
VSS VSS
GPIO36/
SCIRXDA/
XZCS0
VSS
GPIO38/
XWE0
VSS
XRD
GPIO77/
XD2
GPIO74/
XD5
GPIO71/
XD8
GPIO34/
ECAP1/
XREADY
GPIO78/
XD1
GPIO75/
XD4
GPIO72/
XD7
GPIO28/
SCIRXDA/
XZCS6
GPIO37/
ECAP2/
XZCS7
GPIO41/
XA1
GPIO43/
XA3
GPIO35/
SCITXDA/
XR/W
X2 XCLKIN
GPIO40/
XA0
GPIO42/
XA2
GPIO44/
XA4
GPIO45/
XA5
XCLKOUT
GPIO79/
XD0
GPIO76/
XD3
GPIO73/
XD6
GPIO70/
XD9
XWE1
VSS
Figure 6-8. C2834x 256-Ball ZFE Plastic BGA Lower-Right Quadrant (Bottom View)
www.ti.com
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
I TEXAS INSTRUMENTS
6.2 Signal Descriptions
Table 6-1 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral
signals that are listed under them are alternate functions. Some peripheral functions may not be available in all
devices. See Table 5-1 for details. Inputs are not 5-V tolerant. All XINTF pins have a drive strength of 4 mA
(typical). All GPIO pins are I/O/Z, 4-mA drive typical and have an internal pullup, which can be selectively
enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0–
GPIO11 and GPIO58–GPIO63 pins are not enabled at reset. The pullups on GPIO12–GPIO57 and GPIO64–
GPIO87 are enabled upon reset.
Table 6-1. Signal Descriptions
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
JTAG
TRST M7 R8
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal
device operation. An external pulldown resistor is recommended on this pin. The value of this
resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ
resistor generally offers adequate protection. Because this is application-specific, TI recommends
validating each target board for proper operation of the debugger and the application. (I, ↓)
TCK P9 T11 JTAG test clock. An external pullup resistor is required on this pin. A 2.2-kΩ resistor generally offers
adequate protection.(I)
TMS M8 P9 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)
TDI L6 T8 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)
TDO N7 P8 JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK.
EMU0 N9 P10
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Because this is application-specific, TI recommends validating each
each target board for proper operation of the debugger and the application.
EMU1 L9 R10
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Because this is application-specific, TI recommends validating each
target board for proper operation of the debugger and the application.
Clock
XCLKOUT B14 D16
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, one-fourth the frequency, or one-eighth the frequency of SYSCLKOUT. This is controlled
by bit 19 (BY4CLKMODE), bits 18:16 (XTIMCLK), and bit 2 (CLKMODE) in the XINTCNF2 register.
At reset, XCLKOUT = SYSCLKOUT/8. The XCLKOUT signal can be turned off by setting
XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-
impedance state during a reset.
XCLKIN D9 A12
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
the X1 pin must be tied to VSSK. If a crystal/resonator is used (or if an external 1.8-V oscillator is
used to feed clock to X1 pin), this pin must be tied to VSS. (I)
X1 C8 A7
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal may be connected
across X1 and X2. The X1 pin is referenced to the 1.8-V core digital power supply. A 1.8-V external
oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to VSS.
If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to VSSK. (I)
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
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I TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
X2 A8 A9 Internal Oscillator Output. A quartz crystal may be connected across X1 and X2. If X2 is not used it
must be left unconnected. (O)
Reset
XRS P8 T10
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the MCU when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
The output buffer of this pin is an open drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.
XRSIO N8 T9
XRS I/O Control (I) - This pin must be connected to the XRS pin on the target board. When XRS is
low (reset), the level detected on this pin puts all output buffers on the device in high-impedance
mode.
External ADC Interface Signals
EXTSOC1A N1 M2 External ADC SOC Group 1 A Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCA internal signals (O)
EXTSOC1B M3 M3 External ADC SOC Group 1 B Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCB internal signals (O)
EXTSOC2A M2 N1 External ADC SOC Group 2 A Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCA internal signals (O)
EXTSOC2B P1 N2 External ADC SOC Group 2 B Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCB internal signals (O)
EXTSOC3A N2 N3 External ADC SOC Group 3 A Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCA internal signals (O)
EXTSOC3B P2 P2 External ADC SOC Group3 B Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCB internal signals (O)
EXTADCCLK N3 R3 External ADC Clock Signal. Clock for external ADC support, derived from SYSCLK (O)
GPIO and Peripheral Signals
GPIO0
EPWM1A
-
-
B1 D2
General-purpose input/output 0 (I/O/Z)
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
GPIO1
EPWM1B
ECAP6
MFSRB
C1 E1
General-purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
GPIO2
EPWM2A
-
-
F5 E2
General-purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
GPIO3
EPWM2B
ECAP5
MCLKRB
E4 E3
General-purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
GPIO4
EPWM3A
-
-
E2 F1
General-purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
GPIO5
EPWM3B
MFSRA
ECAP1
E3 F2
General-purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
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I TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
F3 F3
General-purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
EPWM4B
MCLKRA
ECAP2
F2 G1
General-purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
Enhanced capture input/output 2 (I/O)
GPIO8
EPWM5A
CANTXB
ADCSOCAO
G4 G2
General-purpose input/output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
ADC start-of-conversion A (O)
GPIO9
EPWM5B
SCITXDB
ECAP3
G2 G3
General-purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
Enhanced capture input/output 3 (I/O)
GPIO10
EPWM6A
CANRXB
ADCSOCBO
G3 H1
General-purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
ADC start-of-conversion B (O)
GPIO11
EPWM6B
SCIRXDB
ECAP4
H3 H2
General-purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB
H2 H3
General-purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB
H4 J2
General-purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14
H5 J3
General-purpose input/output 14 (I/O/Z)
TZ3/ XHOLD
Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface
(XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To
prevent this from happening when TZ3 signal goes active, disable this function by writing
XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3
goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the
code. The XINTF will release the bus when any current access is complete and there are no
pending accesses on the XINTF. (I)
SCITXDB
MCLKXB
SCI-B Transmit (O)
McBSP-B transmit clock (I/O)
GPIO15
K2 K2
General-purpose input/output 15 (I/O/Z)
TZ4/ XHOLDA
Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the
direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is
chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven
active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals
will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released.
External devices should only drive the external bus when XHOLDA is active (low). (I/O)
SCIRXDB
MFSXB
SCI-B receive (I)
McBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5
K4 L1
General-purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
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Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
GPIO17
SPISOMIA
CANRXB
TZ6
J5 L2
General-purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
GPIO18
SPICLKA
SCITXDB
CANRXA
L1 M1
General-purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
Enhanced CAN-A receive (I)
GPIO19
SPISTEA
SCIRXDB
CANTXA
P3 T4
General-purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
Enhanced CAN-A transmit (O)
GPIO20
EQEP1A
MDXA
CANTXB
L4 R4
General-purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
GPIO21
EQEP1B
MDRA
CANRXB
M4 T5
General-purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
GPIO22
EQEP1S
MCLKXA
SCITXDB
N4 R5
General-purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
GPIO23
EQEP1I
MFSXA
SCIRXDB
P4 P5
General-purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
GPIO24
ECAP1
EQEP2A
MDXB
P5 T6
General-purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB
M5 R6
General-purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB
K6 P6
General-purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
GPIO27
ECAP4
EQEP2S
MFSXB
M6 T7
General-purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6
A12 B13
General-purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
GPIO29
SCITXDA
XA19
C3 D1
General-purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18
C2 C2
General-purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
GPIO31
CANTXA
XA17
B2 B3
General-purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
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I TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
P6 R7
General-purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
N6 P7
General-purpose input/output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY
A13 B14
General-purpose input/output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal
GPIO35
SCITXDA
XR/ W
B13 C15
General-purpose input/output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
GPIO36
SCIRXDA
XZCS0
B12 A13
General-purpose input/output 36 (I/O/Z)
SCI-A receive data (I)
External Interface zone 0 chip select (O)
GPIO37
ECAP2
XZCS7
D11 B12
General-purpose input/output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
GPIO38
-
XWE0
C12 E15
General-purpose input/output 38 (I/O/Z)
-
External Interface Write Enable 0 (O). XWE0 defaults back to GPIO38 upon reset, during which
time it will be high-impedance.
GPIO39
-
XA16
A2 B4
General-purpose input/output 39 (I/O/Z)
-
External Interface Address Line 16 (O)
GPIO40
-
XA0
E10 C12
General-purpose input/output 40 (I/O/Z)
-
External Interface Address Line 0
GPIO41
-
XA1
D10 B11
General-purpose input/output 41 (I/O/Z)
-
External Interface Address Line 1 (O)
GPIO42
-
XA2
B10 C11
General-purpose input/output 42 (I/O/Z)
-
External Interface Address Line 2 (O)
GPIO43
-
XA3
A10 B10
General-purpose input/output 43 (I/O/Z)
-
External Interface Address Line 3 (O)
GPIO44
-
XA4
A9 C10
General-purpose input/output 44 (I/O/Z)
-
External Interface Address Line 4 (O)
GPIO45
-
XA5
B9 C9
General-purpose input/output 45 (I/O/Z)
-
External Interface Address Line 5 (O)
GPIO46
-
XA6
E7 B8
General-purpose input/output 46 (I/O/Z)
-
External Interface Address Line 6 (O)
GPIO47
-
XA7
D6 C8
General-purpose input/output 47 (I/O/Z)
-
External Interface Address Line 7 (O)
GPIO48
ECAP5
XD31
SPISIMOD
M10 R11
General-purpose input/output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (O)
SPI-D slave in, master out (I/O)
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Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
GPIO49
ECAP6
XD30
SPISOMID
P10 P11
General-purpose input/output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (O)
SPI-D slave out, master in (I/O)
GPIO50
EQEP1A
XD29
SPICLKD
N10 T12
General-purpose input/output 50 (I/O/Z)
Enhanced QEP 1input A (I)
External Interface Data Line 29 (O)
SPI-D Clock input/output (I/O)
GPIO51
EQEP1B
XD28
SPISTED
N11 R12
General-purpose input/output 51 (I/O/Z)
Enhanced QEP 1input B (I)
External Interface Data Line 28 (O)
SPI-D slave transmit enable input/output (I/O)
GPIO52
EQEP1S
XD27
M11 P12
General-purpose input/output 52 (I/O/Z)
Enhanced QEP 1Strobe (I/O)
External Interface Data Line 27 (O)
GPIO53
EQEP1I
XD26
L11 T13
General-purpose input/output 53 (I/O/Z)
Enhanced QEP1 lndex (I/O)
External Interface Data Line 26 (O)
GPIO54
SPISIMOA
XD25
EQEP3A
P12 R13
General-purpose input/output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (O)
Enhanced QEP3 input A (I)
GPIO55
SPISOMIA
XD24
EQEP3B
N12 P13
General-purpose input/output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (O)
Enhanced QEP3 input B (I)
GPIO56
SPICLKA
XD23
EQEP3S
P13 R14
General-purpose input/output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (O)
Enhanced QEP3 strobe (I/O)
GPIO57
SPISTEA
XD22
EQEP3I
N13 P15
General-purpose input/output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (O)
Enhanced QEP3 index (I/O)
GPIO58
MCLKRA
XD21
EPWM7A
P14 N16
General-purpose input/output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (O)
Enhanced PWM 7 output A and HRPWM channel (O)
GPIO59
MFSRA
XD20
EPWM7B
M13 N15
General-purpose input/output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (O)
Enhanced PWM 7 output B (O)
GPIO60
MCLKRB
XD19
EPWM8A
M14 M16
General-purpose input/output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (O)
Enhanced PWM 8 output A and HRPWM channel (O)
GPIO61
MFSRB
XD18
EPWM8B
L12 M15
General-purpose input/output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (O)
Enhanced PWM8 output B (O)
GPIO62
SCIRXDC
XD17
EPWM9A
L13 M14
General-purpose input/output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (O)
Enhanced PWM9 output A and HRPWM channel (O)
GPIO63
SCITXDC
XD16
EPWM9B
K13 L16
General-purpose input/output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (O)
Enhanced PWM9 output B (O)
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Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
GPIO64
-
XD15
K12 L15
General-purpose input/output 64 (I/O/Z)
-
External Interface Data Line 15 (O)
GPIO65
-
XD14
K14 L14
General-purpose input/output 65 (I/O/Z)
-
External Interface Data Line 14 (O)
GPIO66
-
XD13
J11 K15
General-purpose input/output 66 (I/O/Z)
-
External Interface Data Line 13 (O)
GPIO67
-
XD12
J12 K14
General-purpose input/output 67 (I/O/Z)
-
External Interface Data Line 12 (O)
GPIO68
-
XD11
J13 J15
General-purpose input/output 68 (I/O/Z)
-
External Interface Data Line 11 (O)
GPIO69
-
XD10
H13 J14
General-purpose input/output 69 (I/O/Z)
-
External Interface Data Line 10 (O)
GPIO70
-
XD9
H12 H16
General-purpose input/output 70 (I/O/Z)
-
External Interface Data Line 9 (O)
GPIO71
-
XD8
G12 H15
General-purpose input/output 71 (I/O/Z)
-
External Interface Data Line 8 (O)
GPIO72
-
XD7
G13 H14
General-purpose input/output 72 (I/O/Z)
-
External Interface Data Line 7 (O)
GPIO73
-
XD6
F14 G16
General-purpose input/output 73 (I/O/Z)
-
External Interface Data Line 6 (O)
GPIO74
-
XD5
F13 G15
General-purpose input/output 74 (I/O/Z)
-
External Interface Data Line 5 (O)
GPIO75
-
XD4
F12 G14
General-purpose input/output 75 (I/O/Z)
-
External Interface Data Line 4 (O)
GPIO76
-
XD3
E13 F16
General-purpose input/output 76 (I/O/Z)
-
External Interface Data Line 3 (O)
GPIO77
-
XD2
E11 F15
General-purpose input/output 77 (I/O/Z)
-
External Interface Data Line 2 (O)
GPIO78
-
XD1
F10 F14
General-purpose input/output 78 (I/O/Z)
-
External Interface Data Line 1 (O)
GPIO79
-
XD0
C14 E16
General-purpose input/output 79 (I/O/Z)
-
External Interface Data Line 0 (O)
GPIO80
-
XA8
E6 B7
General-purpose input/output 80 (I/O/Z)
-
External Interface Address Line 8 (O)
GPIO81
-
XA9
C5 C7
General-purpose input/output 81 (I/O/Z)
-
External Interface Address Line 9 (O)
GPIO82
-
XA10
A5 B6
General-purpose input/output 82 (I/O/Z)
-
External Interface Address Line 10 (O)
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Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
GPIO83
-
XA11
B5 C6
General-purpose input/output 83 (I/O/Z)
-
External Interface Address Line 11 (O)
GPIO84
-
XA12
D5 A5
General-purpose input/output 84 (I/O/Z)
-
External Interface Address Line 12 (O)
GPIO85
-
XA13
D4 B5
General-purpose input/output 85 (I/O/Z)
-
External Interface Address Line 13 (O)
GPIO86
-
XA14
A3 C5
General-purpose input/output 86 (I/O/Z)
-
External Interface Address Line 14 (O)
GPIO87
-
XA15
B3 A4
General-purpose input/output 87 (I/O/Z)
-
External Interface Address Line 15 (O)
XRD A14 D15 External Interface Read Enable (O). The XRD pin is high-impedance on reset. It stays that way as
long as the XINTF clock is turned off (which happens on reset).
XWE1 C13 E14 External Memory Interface Write Enable for Upper 16-bits (O). The XWE1 pin is high-impedance on
reset. It stays that way as long as the XINTF clock is turned off (which happens on reset).
CPU and I/O Power Pins
VDD18 E8 A6 Oscillator and PLL Power Pin (1.8 V)
VDD18 C7 A11
VSSK B8 A8 Oscillator Kelvin Reference Ground. This pin should not be connected to Vss. See Figure 8-29
through Figure 8-31 for proper application board connections.
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Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
VDD D1 C1
CPU and logic digital power pins (1.1 V/1.2 V)
VDD E1 C16
VDD G1 E6
VDD K3 E7
VDD M1 E8
VDD N5 E9
VDD P7 E10
VDD J3 E11
VDD J4 F5
VDD K9 F12
VDD L10 G5
VDD N14 G12
VDD K11 H5
VDD H11 H12
VDD H14 J5
VDD G10 J12
VDD E12 K3
VDD D12 K5
VDD C11 K12
VDD C10 L3
VDD B7 L5
VDD C6 L12
VDD E5 M6
VDD C4 M7
VDD M8
VDD M9
VDD M10
VDD M11
VDD P1
VDD P16
VDDIO D3 A3
Digital I/O power pins (3.3 V)
VDDIO F1 A14
VDDIO J1 B9
VDDIO L2 D5
VDDIO K5 D6
VDDIO K7 D8
VDDIO K8 D11
VDDIO P11 D12
VDDIO L14 E4
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Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
VDDIO J14 E13
Digital I/O power pins
VDDIO F11 F4
VDDIO D14 F13
VDDIO A11 J1
VDDIO C9 J4
VDDIO D7 J13
VDDIO B6 J16
VDDIO B4 L4
VDDIO L13
VDDIO M4
VDDIO M13
VDDIO N5
VDDIO N6
VDDIO N8
VDDIO N11
VDDIO N12
VDDIO R9
VDDIO T3
VDDIO T14
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Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
VSS D2 A1
Digital ground pins
VSS F4 A2
VSS G5 A10
VSS H1 A15
VSS J2 A16
VSS K1 B1
VSS L3 B2
VSS L5 B15
VSS L7 B16
VSS L8 C3
VSS M9 C4
VSS K10 C13
VSS M12 C14
VSS J10 D3
VSS H10 D4
VSS G14 D7
VSS G11 D9
VSS E14 D10
VSS D13 D13
VSS B11 D14
VSS E9 E5
VSS D8 E12
VSS A7 F6
VSS A6 F7
VSS A4 F8
VSS F9
VSS F10
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I TEXAS INSTRUMENTS
Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
VSS F11
Digital ground pins
VSS G4
VSS G6
VSS G7
VSS G8
VSS G9
VSS G10
VSS G11
VSS G13
VSS H4
VSS H6
VSS H7
VSS H8
VSS H9
VSS H10
VSS H11
VSS H13
VSS J6
VSS J7
VSS J8
VSS J9
VSS J10
VSS J11
VSS K1
VSS K4
VSS K6
VSS K7
VSS K8
VSS K9
VSS K10
VSS K11
VSS K13
VSS K16
VSS L6
VSS L7
VSS L8
VSS L9
VSS L10
VSS L11
VSS M5
VSS M12
VSS N4
VSS N7
VSS N9
VSS N10
VSS N13
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Table 6-1. Signal Descriptions (continued)
NAME ZHH
BALL #
ZFE
BALL # DESCRIPTION
VSS N14
Digital ground pins
VSS P3
VSS P4
VSS P14
VSS R1
VSS R2
VSS R15
VSS R16
VSS T1
VSS T2
VSS T15
VSS T16
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7 Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.
7.1 Absolute Maximum Ratings (1) (2)
MIN MAX UNIT
Supply voltage VDDIO with respect to VSS –0.3 4
VVDD with respect to VSS –0.3 1.5
VDD18 with respect to VSS –0.3 2.4
Input voltage VIN (3.3 V) –0.3 4 V
VIN (1.8 V) –0.3 2.4
Output voltage VO–0.3 4 V
Input clamp current IIK (VIN < 0 or VIN > VDDIO)(3) –20 20 mA
Output clamp current IOK (VO < 0 or VO > VDDIO) –20 20 mA
Junction temperature TJ (4) –40 150 °C
Storage temperature Tstg (4) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA.
(4) One or both of the following conditions may result in a reduction of overall device life:
long-term high-temperature storage
extended use at maximum temperature
For additional information, see Semiconductor and IC Package Thermal Metrics.
7.2 ESD Ratings – Automotive
VALUE UNIT
TMS320C2834x in ZFE Package
V(ESD) Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1) ±2000
V
Charged-device model (CDM), per AEC Q100-011
All pins ±500
Corner pins on 256-ball
ZFE: A1, A16, T1, T16
±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance wit hthe ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings – Commercial
VALUE UNIT
TMS320C2834x in ZHH Package
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
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7.4 Recommended Operating Conditions
MIN NOM MAX UNIT
Device supply voltage, I/O, VDDIO 3.14 3.3 3.46 V
Device supply voltage CPU, VDD
300-MHz devices 1.14 1.2 1.26 V
200-MHz devices 1.05 1.1 1.16
Supply ground, VSS, VSSIO 0 V
Oscillator supply ground, VSSK 0 V
PLL/oscillator supply, VDD18 1.71 1.8 1.89 V
Device clock frequency (system clock),
fSYSCLKOUT
C28346/C28344/C28342
(VDD = 1.2 V ± 5%)
2 300
MHz
C28345/C28343/C28341
(VDD = 1.1 V ± 5%)
2 200
High-level input voltage, VIH (3.3 V) 2 VDDIO + 0.3 V
High-level input voltage, VIH (1.8 V) 0.7 * VDD18 V
Low-level input voltage, VIL (3.3 V) VSS – 0.3 0.8 V
Low-level input voltage, VIL (1.8 V) 0.3 * VDD18 V
High-level output source current,
VOH = 2.4 V, IOH
All I/Os –4 mA
Low-level output sink current,
VOL = VOL MAX, IOL
All I/Os 4 mA
Junction temperature, TJ (1)
T version –40 105
°C
S version –40 125
Q version
(AEC Q100 Qualification)
–40 125
(1) TA (Ambient temperature) is product- and application-dependent and can go up to the specified TJ maximum of the device. See
Section 7.8, Thermal Design Considerations.
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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7.5 Power Consumption Summary
7.5.1 TMS320C28346/C28344 (1) Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
MODE TEST CONDITIONS
IDD IDDIO (2) IDD18
25°C 105°C 125°C 25°C 105°C 125°C 25°C 105°C 125°C
Typical Operational
The following peripheral clocks are
enabled:
ePWM1, ePWM2, ePWM3,
ePWM4, ePWM5, ePWM6,
ePWM7, ePWM8, ePWM9
eCAP1, eCAP2, eCAP3
eQEP1, eQEP2, eQEP3
• eCAN-A
SCI-A, SCI-B (FIFO mode)
SPI-A (FIFO mode)
• McBSP-A
• I2C
• XINTF
• DMA
CPU-Timer 0, CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at
300 kHz.
All I/O pins are left unconnected.
XCLKOUT is turned off. Pullups on
output pins and XINTF pins are
disabled.(3)
335 mA 555 mA 740 mA 75 mA 75 mA 80 mA 50 mA 47 mA 45 mA
IDLE XCLKOUT is turned off.
Peripheral clocks are off. 205 mA 425 mA 610 mA 15 mA 15 mA 18 mA 50 mA 47 mA 45 mA
STANDBY Peripheral clocks are off. 140 mA 360 mA 545 mA 15 mA 15 mA 18 mA 50 mA 47 mA 45 mA
HALT Peripheral clocks are off.
Input clock is disabled.(4) 135 mA 355 mA 540 mA 15 mA 15 mA 18 mA 550 μA 550 μA 550 μA
(1) The IDD numbers in this table are valid for the TMS320C28346 and TMS320C28344 devices only. For the TMS320C28342 device,
subtract the IDD current numbers for those peripherals that do not exist on this device (see Table 7-1) from the IDD current numbers
shown in this table.
(2) IDDIO current is dependent on the electrical loading on the I/O pins.
(3) The following is done in a loop:
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Floating-point multiplication and addition are performed.
32-bit read/write of the XINTF is performed.
DMA channels 1 and 2 transfer data from SARAM to SARAM.
GPIO19 is toggled.
(4) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
Note
The IDD numbers in Section 7.5.1 are valid for the TMS320C28346 and TMS320C28344 devices only.
For the TMS320C28342 device, subtract the IDD current numbers for those peripherals that do not
exist on this device (see Table 7-1) from the IDD current numbers shown in Section 7.5.1.
Note
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from
being used at the same time. This is because more than one peripheral function may share an I/O pin.
It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a
configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
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7.5.2 TMS320C28345/C28343 (1) Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
MODE TEST CONDITIONS
IDD IDDIO (2) IDD18
25°C 105°C 125°C 25°C 105°C 125°C 25°C 105°C 125°C
Typical operation
The following peripheral clocks are
enabled:
ePWM1, ePWM2, ePWM3,
ePWM4, ePWM5, ePWM6,
ePWM7, ePWM8, ePWM9
eCAP1, eCAP2, eCAP3
eQEP1, eQEP2, eQEP3
• eCAN-A
SCI-A, SCI-B (FIFO mode)
SPI-A (FIFO mode)
• McBSP-A
• I2C
• XINTF
• DMA
CPU-TImers 0, CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at 200 kHz.
All I/O pins are left unconnected.
XCLKOUT is turned off. Pullups on
output pins and XINTF pins are
disabled.(3)
200 mA 380 mA 500 mA 45 mA 45 mA 45 mA 45 mA 43 mA 40 mA
IDLE Peripheral clocks are off. XCLKOUT is
turned off. 95 mA 275 mA 395 mA 15 mA 15 mA 18 mA 45 mA 43 mA 40 mA
STANDBY Peripheral clocks are off. 45 mA 225 mA 345 mA 15 mA 15 mA 18 mA 45 mA 43 mA 40 mA
HALT Peripheral clocks are off. Input clock is
disabled.(4) 40 mA 220 mA 340 mA 15 mA 15 mA 18 mA 550 μA 550 μA 550 μA
(1) The IDD numbers in this table are valid for the TMS320C28345 and TMS320C28343 devices only. For the TMS320C28341 device,
subtract the IDD current numbers for those peripherals that do not exist on this device (see Table 7-1) from the IDD current numbers
shown in this table.
(2) IDDIO current is dependent on the electrical loading on the I/O pins.
(3) The following is done in a loop:
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Floating-point multiplication and addition are performed.
32-bit read/write of the XINTF is performed.
DMA channels 1 and 2 transfer data from SARAM to SARAM.
GPIO19 is toggled.
(4) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
Note
The IDD numbers in Section 7.5.2 are valid for the TMS320C28345 and TMS320C28343 devices only.
For the TMS320C28341 device, subtract the IDD current numbers for those peripherals that do not
exist on this device (see Table 7-1) from the IDD current numbers shown in Section 7.5.2.
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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7.5.3 Reducing Current Consumption
Methods of reducing current consumption include the following:
Turn off the clock to any peripheral module that is not used in a given application because each peripheral
unit has an individual clock-enable bit. Table 7-1 indicates the typical reduction in current consumption
achieved by turning off the clocks.
Use any one of the three low-power modes to reduce current even further.
Turn off XCLKOUT, reducing IDDIO current consumption by 15 mA (typical).
Disable the pullups on pins that assume an output function and on XINTF pins for significant savings in IDDIO.
Note
The TMS320C2834x devices are manufactured in a high-performance process node. Compared to
the previous generation of the C28x devices, this process has more leakage current. Leakage current
is significantly impacted by the operating temperature, and the increase in current with temperature is
nonlinear. The total power for a given operating condition includes switching/active power plus
leakage power. Low-power HALT mode power is due to the leakage current alone.
Figure 7-1 shows the typical leakage current across temperature.
Figure 7-1. Temperature Versus Leakage Current (Typical)
Table 7-1. Typical Current Consumption by Various
Peripherals (1)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION (mA)
I2C 5
eQEP 5
ePWM 3
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I TEXAS INSTRUMENTS
Table 7-1. Typical Current Consumption by Various
Peripherals (1) (continued)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION (mA)
eCAP 1
SCI 4
SPI 4
eCAN 2
McBSP 8
CPU-Timer 1
XINTF 4(2)
DMA 7
FPU 8
(1) All peripheral clocks (except CPU timer clocks) are disabled
upon reset. Writing to or reading from peripheral registers is
possible only after the peripheral clocks are turned on.
(2) Operating the XINTF bus has a significant effect on IDDIO
current. It will increase considerably based on the following:
How many address/data pins toggle from one cycle to
another
How fast they toggle
Whether 16-bit or 32-bit interface is used and
The load on these pins.
Whether internal pullups are enabled on the XINTF pins.
7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = IOH MAX 2.4 V
IOH = 50 μA VDDIO – 0.2
VOL Low-level output voltage IOL = IOL MAX 0.4 V
IIL
Input current
(low level)
Pin with pullup
enabled VDDIO = 3.3 V, VIN = 0 V All I/Os (including XRS) –190 –100
μA
Pin with pulldown
enabled VDDIO = 3.3 V, VIN = 0 V ±15
IIH
Input current
(high level)
Pin with pullup
enabled VDDIO = 3.3 V, VIN = VDDIO ±3
μA
Pin with pulldown
enabled VDDIO = 3.3 V, VIN = VDDIO 100 175
IOZ
Output current, pullup or pulldown
disabled VO = VDDIO or 0 V ±15 μA
CIInput capacitance 2 pF
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
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7.7 Thermal Resistance Characteristics
7.7.1 ZHH Package
°C/W(1) (2) AIR FLOW (lfm)(3)
JC Junction-to-case 10.3 0
JB Junction-to-board 21.2 0
JA
(High k PCB) Junction-to-free air
40.8 0
32.4 150
31.0 250
29.1 500
PsiJT Junction-to-package top
0.4 0
0.5 150
0.6 250
0.8 500
PsiJB Junction-to-board
21.0 0
20.4 150
20.2 250
19.9 500
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
7.7.2 ZFE Package
°C/W(1) (2) AIR FLOW (lfm)(3)
JC Junction-to-case 14 0
JB Junction-to-board 13.9 0
JA
(High k PCB) Junction-to-free air
30 0
21.8 150
20.6 250
19.1 500
PsiJT Junction-to-package top
1.24 0
2.63 150
3.15 250
4.05 500
PsiJB Junction-to-board
14 0
13.6 150
13.5 250
13.4 500
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
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JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC package thermal metrics helps to understand the thermal metrics and
definitions.
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
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TEXAS INSTRUMENTS
7.9 Timing and Switching Characteristics
7.9.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
f fall time X Unknown, changing, or don't care level
h hold time Z High impedance
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)
7.9.1.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
7.9.1.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Transmission Line
4.0 pF 1.85 pF
Z0 = 50 )
Tester Pin Electronics Data Sheet Timing Reference Point
Output
Under
Test
42 3.5 nH
Device Pin(B)
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 7-2. 3.3-V Test Load Circuit
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7.9.1.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available. Section 7.9.1.3.1 and Section 7.9.1.3.2 list the cycle times of various clocks.
7.9.1.3.1 Clocking and Nomenclature (300-MHz Devices)
MIN NOM MAX UNIT
On-chip oscillator clock (crystal/resonator–X1/X2) tc(OSC), Cycle time 33.3 125 ns
Frequency 8 30 MHz
XCLKIN(5)
PLL enabled tc(CI), Cycle time (C8) 6.67 50 ns
Frequency 2 150 MHz
PLL disabled tc(CI), Cycle time (C8) 6.67 250 ns
Frequency 4 150 MHz
X1(5)
PLL enabled tc(CI), Cycle time (C8) 10 50 ns
Frequency 2 100 MHz
PLL disabled tc(CI), Cycle time (C8) 10 250 ns
Frequency 4 100 MHz
SYSCLKOUT tc(SCO), Cycle time 3.33 500 ns
Frequency 2 300 MHz
XCLKOUT tc(XCO), Cycle time 13.3 2000 ns
Frequency 0.5 75(4) MHz
HSPCLK/EXTADCCLK(2) tc(HCO), Cycle time 25 ns
Frequency 40 MHz
LSPCLK(1) tc(LCO), Cycle time 6.67 13.3(3) ns
Frequency 75(3) 150 MHz
(1) Lower LSPCLK and HSPCLK will reduce device power consumption.
(2) This frequency is limited by GPIO switching characteristics.
(3) This is the value if SYSCLKOUT = 300 MHz.
(4) Although the maximum XCLKOUT frequency is 75 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
(5) The input clock frequency and PLLCR[DIV] values should be chosen such that the output frequency of the PLL(VCOCLK) lies between
400 MHz to 600 MHz.
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
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7.9.1.3.2 Clocking and Nomenclature (200-MHz Devices)
MIN NOM MAX UNIT
On-chip oscillator clock (crystal/resonator–X1/X2) tc(OSC), Cycle time 33.3 125 ns
Frequency 8 30 MHz
XCLKIN(5)
PLL enabled tc(CI), Cycle time (C8) 6.67 50 ns
Frequency 2 150 MHz
PLL disabled tc(CI), Cycle time (C8) 6.67 250 ns
Frequency 4 150 MHz
X1(5)
PLL enabled tc(CI), Cycle time (C8) 10 50 ns
Frequency 2 100 MHz
PLL disabled tc(CI), Cycle time (C8) 10 250 ns
Frequency 4 100 MHz
SYSCLKOUT tc(SCO), Cycle time 5 500 ns
Frequency 2 200 MHz
XCLKOUT tc(XCO), Cycle time 13.3 2000 ns
Frequency 0.5 75(4) MHz
HSPCLK/EXTADCCLK(1) tc(HCO), Cycle time 8 ns
Frequency 40 MHz
LSPCLK(2) tc(LCO), Cycle time 10 20(3) ns
Frequency 50(3) 100 MHz
(1) This frequency is limited by GPIO switching characteristics.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the value if SYSCLKOUT = 200 MHz.
(4) Although the maximum XCLKOUT frequency is 75 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
(5) The input clock frequency and PLLCR[DIV] values should be chosen such that the output frequency of the PLL(VCOCLK) lies between
400 MHz to 600 MHz.
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7.9.2 Power Sequencing
No special requirements are placed on the power up/down sequence of the various power pins to ensure the
correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of the
I/O pins are powered prior to the 1.1-V/1.2-V transistors, it is possible for the output buffers to turn on, causing a
glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or simultaneously
with the VDDIO pins, ensuring that the VDD pins have reached 0.7-V before the VDDIO pins reach 0.7 V. The 1.8-V
rail for the PLL and oscillator logic can be powered up along with VDD/VDDIO rails. The 1.8-V rail must be
powered even if the PLL is not used. It should never be left unpowered. In any configuration, all the rails should
ramp up within tpup (5 ms, typical) to allow early stability of clocks and IOs.
There is a requirement on the XRS pin:
During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable. This is to enable the
entire device to start from a known condition.
No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin before powering up
the device. Voltages applied to pins on an unpowered device can bias internal P-N junctions in unintended ways
and produce unpredictable results.
7.9.2.1 Power Management and Supervisory Circuit Solutions
LDO selection depends on the total power consumed in the end application. Go to the Power Management page
for a list of TI power management ICs. Click the Reference designs tab for specific power management
reference designs.
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
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{5‘ TEXAS INSTRUMENTS
tw(RSL1)
th(boot-mode)(B)
XCLKIN
X1/X2
XRS
Boot-Mode
Pins
V (1.2V/1.1V)
DD
XCLKOUT
I/OPins
User-CodeDependent
User-CodeDependent
Boot-ROMExecutionStarts Peripheral/GPIOFunction
BasedonBootCode
GPIOPinsasInput
OSCCLK/64 (A)
GPIOPinsasInput(StateDependsonInternalPU/PD)
tOSCST
User-CodeDependent
Address/Data/
Control
(Internal)
Address/DataValid.InternalBoot-ROMCodeExecutionPhase
User-CodeExecutionPhase
td(EX)
OSCCLK/16
V (3.3V)
DDIO
V (1.8V)
DD18
tpup
(C)
A. Upon power up, SYSCLKOUT is OSCCLK/8. Because the XTIMCLK, CLKMODE, and BY4CLKMODE bits in the XINTFCNF2 register
come up with a reset state of 1, SYSCLKOUT is further divided by 8 before it applies to XCLKOUT. This explains why XCLKOUT =
OSCCLK/64 during this phase. Subsequently, boot ROM changes SYSCLKOUT to OSCLK/2. Because the XTIMCLK register is
unchanged by the boot ROM, XCLKOUT is OSCCLK/16 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
C. See Section 7.9.2 for requirements to ensure a high-impedance state for GPIO pins during power up.
Figure 7-3. Power-on Reset
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fl TEXAS INSTRUMENTS \ \—/1\+/\_«~_/\+/\_/ \_/w\+/\+/\+/\_/ _/ —/ \ X/ X W X/
7.9.2.2 Reset ( XRS) Timing Requirements
MIN NOM MAX UNIT
tw(RSL1) (1) Pulse duration, stable input clock to XRS high 64tc(OSCCLK) cycles
tw(RSL2) Pulse duration, XRS low Warm reset 64tc(OSCCLK) cycles
tw(WDRS)
Pulse duration, reset pulse generated by
watchdog 512tc(OSCCLK) cycles
td(EX) Delay time, address/data valid after XRS high 32tc(OSCCLK) cycles
tOSCST (2) Oscillator start-up time 1 10 ms
th(boot-mode) Hold time for boot-mode pins 200tc(OSCCLK) cycles
tpup Power-up time 5 ms
(1) In addition to the tw(RSL1) requirement, XRS must be low until VDD has reached the minimum operating voltage.
(2) Dependent on crystal/resonator and board design.
th(boot-mode)(A)
tw(RSL2)
XCLKIN
X1/X2
XRS
Boot-Mode
Pins
XCLKOUT
I/O Pins
Address/Data/
Control
(Internal)
Boot-ROM Execution Starts
User-Code Execution Starts
User-Code Dependent
User-Code Execution Phase
(Don’t Care)
User-Code Dependent
User-Code Execution
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
GPIO Pins as Input Peripheral/GPIO Function
td(EX)
OSCCLK * 5
OSCCLK/8
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 7-4. Warm Reset
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TEXAS INSTRUMENTS T T
Figure 7-5 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0003
and SYSCLKOUT = OSCCLK × 2. The PLLCR is then written with 0x0007 (setting for OSCCLK × 8). Right after
the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2.
After the PLL lock-up is complete (which takes 2600 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK × 4.
OSCCLK
SYSCLKOUT
WritetoPLLCR
OSCCLK*2
(CurrentCPU
Frequency)
OSCCLK/2
(CPUFrequencyWhilePLLisStabilizing
WiththeDesiredFrequency.ThisPeriod
(PLLLock-upTime,tp)is
2600OSCCLKCyclesLong.)
OSCCLK*4
(ChangedCPUFrequency)
Figure 7-5. Example of Effect of Writing Into PLLCR Register
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I TEXAS INSTRUMENTS * K #7054 1 \ i r ‘Hc. H u‘ r as +—~ \ \ ‘ 1 1 H—* (:5 ‘ Hum \ x H \
7.9.3 Clock Requirements and Characteristics
7.9.3.1 XCLKIN/X1 Timing Requirements – PLL Enabled
NO. MIN MAX UNIT
C9 tf(CI) Fall time, XCLKIN(1) 4 ns
C10 tr(CI) Rise time, XCLKIN(1) 4 ns
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) (1) 40% 60%
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) (1) 40% 60%
(1) This applies to the X1 pin also.
7.9.3.2 XCLKIN/X1 Timing Requirements – PLL Disabled
NO. MIN MAX UNIT
C9 tf(CI) Fall time, XCLKIN(1) 2 ns
C10 tr(CI) Rise time, XCLKIN(1) 2 ns
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) (1) 45% 55%
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) (1) 45% 55%
(1) This applies to the X1 pin also.
The possible configuration modes are shown in Table 8-34.
7.9.3.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
NO. PARAMETER MIN TYP MAX UNIT
C1 tc(XCO) Cycle time, XCLKOUT 13.3 ns
C3 tf(XCO) Fall time, XCLKOUT 2 ns
C4 tr(XCO) Rise time, XCLKOUT 2 ns
C5 tw(XCOL) Pulse duration, XCLKOUT low H – 2 H + 2 ns
C6 tw(XCOH) Pulse duration, XCLKOUT high H – 2 H + 2 ns
tpPLL lock time 2600tc(OSCCLK) (3) cycles
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
7.9.3.4 Timing Diagram
C4
C3
XCLKOUT(B)
XCLKIN(A)
C5
C9
C10
C1
C8
C6
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate
the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 7-6. Clock Timing
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I TEXAS INSTRUMENTS
7.9.4 Peripherals
7.9.4.1 General-Purpose Input/Output (GPIO)
7.9.4.1.1 GPIO - Output Timing
7.9.4.1.1.1 General-Purpose Output Switching Characteristics
PARAMETER MIN MAX UNIT
tr(GPO) Rise time, GPIO switching low to high All GPIOs 11 ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 11 ns
tfGPO Toggling frequency, GPO pins 40 MHz
GPIO
tr(GPO)
tf(GPO)
Figure 7-7. General-Purpose Output Timing
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w TEXAS INSTRUMENTS HHMHMHMMMMH Qualifier
7.9.4.1.2 GPIO - Input Timing
7.9.4.1.2.1 General-Purpose Input Timing Requirements
MIN MAX UNIT
tw(SP) Sampling period QUALPRD = 0 1tc(SCO) cycles
QUALPRD ≠ 0 2tc(SCO) * QUALPRD
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
tw(GPI) (2) Pulse duration, GPIO low/high Synchronous mode 2tc(SCO) cycles
With input qualifier tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
GPIO Signal
1
Sampling Window
Output From
Qualifier
1 1 1111111110000000 000
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C))
(A)
GPxQSELn = 1,0 (6 samples)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
(D)
tw(SP)
tw(IQSW)
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in
2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to
occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 7-8. Sampling Mode
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I TEXAS INSTRUMENTS s /\_/\+/\_/\_/\_
7.9.4.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using three samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using six samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
GPIOxn
SYSCLK
tw(GPI)
Figure 7-9. General-Purpose Input Timing
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I TEXAS INSTRUMENTS Add ‘Dt 5:34.53 x x x x x x: \ \ k7 4A — WAKEINTW 4‘ y
7.9.4.1.4 Low-Power Mode Wakeup Timing
The wakeup signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of
the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
Section 7.9.4.1.4.1 shows the timing requirements, Section 7.9.4.1.4.2 shows the switching characteristics, and
Figure 7-10 shows the timing diagram for IDLE mode.
7.9.4.1.4.1 IDLE Mode Timing Requirements (1)
MIN MAX UNIT
tw(WAKE-INT) Pulse duration, external wake-up signal Without input qualifier 2tc(SCO) cycles
With input qualifier 5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.1.4.2 IDLE Mode Switching Characteristics (1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(WAKE-IDLE)
Delay time, external wake signal to
program execution resume (2)
Wake-up from SARAM
Without input qualifier 20tc(SCO)
cycles
With input qualifier 20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
7.9.4.1.4.3 IDLE Mode Timing Diagram
WAKE INT(A)
XCLKOUT
Address/Data
(internal)
td(WAKE−IDLE)
tw(WAKE−INT)
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 7-10. IDLE Entry and Exit Timing
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I TEXAS INSTRUMENTS 4 F H 4’1 % m‘ 1 rim)!» hi 44‘ p7 4. ‘ \ 20‘ K )6 sur’I’DBv 1 STANDBY 1 )6 Flushing pipeline ‘ ‘ ‘ ‘ Wake-up Signal X1/X2 or X1m XCLKIN XCLKOUT \ \ ’ H—H MIDLE—xcou
7.9.4.1.4.4 STANDBY Mode Timing Requirements
MIN MAX UNIT
tw(WAKE-INT)
Pulse duration, external
wake-up signal
Without input qualification 3tc(OSCCLK) cycles
With input qualification(1) (2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
7.9.4.1.4.5 STANDBY Mode Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(IDLE-XCOL)
Delay time, IDLE instruction
executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
td(WAKE-STBY)
Delay time, external wake signal to
program execution resume(1)
Wake up from SARAM
Without input qualifier 100tc(SCO)
cycles
With input qualifier 100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
7.9.4.1.4.6 STANDBY Mode Timing Diagram
tw(WAKE-INT)
td(WAKE-STBY)
td(IDLEXCOL)
Wake-up
Signal
X1/X2 or
X1 or
XCLKIN
XCLKOUT
STANDBY Normal ExecutionSTANDBY
Flushing Pipeline
(A)
(B)
(C)
(D)
(E)
(F)
Device
Status
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for 32 cycles before being turned off. This delay enables the CPU
pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this
number then it will fail. TI recommends entering STANDBY mode from SARAM without an XINTF access in progress.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 7-11. STANDBY Entry and Exit Timing Diagram
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I TEXAS INSTRUMENTS \ \ Device ‘ ‘ xx xx ‘ ‘ , n XR \\ ‘ ‘ \ \ / Wake-up LaLe \ |_ \ \ \ \ \ \ \ H—hr thDLE—xcm.)
7.9.4.1.4.7 HALT Mode Timing Requirements
MIN MAX UNIT
tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) (1) cycles
tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles
(1) See Section 7.9.2.2 for an explanation of toscst.
7.9.4.1.4.8 HALT Mode Switching Characteristics
PARAMETER MIN MAX UNIT
td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
tpPLL lock-up time 2600tc(OSCCLK) cycles
td(WAKE-HALT)
Delay time, PLL lock to program execution resume
Wake up from SARAM 35tc(SCO) cycles
7.9.4.1.4.9 HALT Mode Timing Diagram
td(IDLEXCOL)
X1/X2
or XCLKIN
XCLKOUT
HALT HALT
Wake-up Latency
Flushing Pipeline
td(WAKE−HALT)
(A)
(B)
(C)
(D)(E)
Device
Status
(F) (H)
(G)
PLL Lock-up Time Normal
Execution
tw(WAKE-GPIO) tp
GPIOn
Oscillator Start-up Time
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for 32 cycles before oscillator is turned off and the CLKIN to the core is
stopped. This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress
and its access time is longer than this number then it will fail. It is recommended to enter HALT mode from SARAM without an XINTF
access in progress.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be
taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 2,600 OSCCLK (X1/X2 or X1 or XCLKIN) cycles.
G. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after
a latency.
H. Normal operation resumes.
Figure 7-12. HALT Wakeup Using GPIOn
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I TEXAS INSTRUMENTS
7.9.4.2 Enhanced Control Peripherals
7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1–6. Section 7.9.4.2.1.1 shows the ePWM timing requirements and
Section 7.9.4.2.1.2, ePWM switching characteristics.
7.9.4.2.1.1 ePWM Timing Requirements (1)
MIN MAX UNIT
tw(SYCIN) Sync input pulse width
Asynchronous 2tc(SCO)
cyclesSynchronous 2tc(SCO)
With input qualifier 1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.2.1.2 ePWM Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(PWM) Pulse duration, PWMx output high/low 20 ns
tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles
td(PWM)tza
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low no pin load 25 ns
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns
7.9.4.2.2 Trip-Zone Input Timing
PWM(B)
TZ(A)
SYSCLK
tw(TZ)
td(TZ-PWM)HZ
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-13. PWM Hi-Z Characteristics
7.9.4.2.2.1 Trip-Zone Input Timing Requirements (1)
MIN MAX UNIT
tw(TZ) Pulse duration, TZx input low
Asynchronous 1tc(SCO)
cyclesSynchronous 2tc(SCO)
With input qualifier 1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
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7.9.4.2.3 High-Resolution PWM Timing
Section 7.9.4.2.3.1 shows the high-resolution PWM switching characteristics.
7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
MIN TYP MAX UNIT
Micro Edge Positioning (MEP) step size(1) VDD = 1.2 V 55 120 ps
VDD = 1.1 V 65 140 ps
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
7.9.4.2.4 Enhanced Capture (eCAP) Timing
Section 7.9.4.2.4.1 shows the eCAP timing requirement and Section 7.9.4.2.4.2 shows the eCAP switching
characteristics.
7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements (1)
MIN MAX UNIT
tw(CAP) Capture input pulse width
Asynchronous 2tc(SCO)
cyclesSynchronous 2tc(SCO)
With input qualifier 1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.2.4.2 eCAP Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(APWM) Pulse duration, APWMx output high/low 20 ns
7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
Section 7.9.4.2.5.1 shows the eQEP timing requirement and Section 7.9.4.2.5.2 shows the eQEP switching
characteristics.
7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)
MIN MAX UNIT
tw(QEPP) QEP input period Asynchronous(2)/synchronous 2tc(SCO) cycles
With input qualifier 2[1tc(SCO) + tw(IQSW)]
tw(INDEXH) QEP Index Input High time Asynchronous(2)/synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW)
tw(INDEXL) QEP Index Input Low time Asynchronous(2)/synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW)
tw(STROBH) QEP Strobe High time Asynchronous(2)/synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW)
tw(STROBL) QEP Strobe Input Low time Asynchronous(2)/synchronous 2tc(SCO) cycles
With input qualifier 2tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) Refer to the TMS320C2834x Delfino™ MCUs Silicon Errata for limitations in the asynchronous mode.
7.9.4.2.5.2 eQEP Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles
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PARAMETER TEST CONDITIONS MIN MAX UNIT
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync
output 6tc(SCO) cycles
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7.9.4.2.6 ADC Start-of-Conversion Timing
7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
PARAMETER MIN MAX UNIT
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO )cycles
7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
ADCSOCAO
or
ADCSOCBO
tw(ADCSOCL)
Figure 7-14. ADCSOCAO or ADCSOCBO Timing
7.9.4.3 External Interrupt Timing
7.9.4.3.1 External Interrupt Timing Requirements (1)
MIN MAX UNIT
tw(INT) (2) Pulse duration, INT input low/high Synchronous 1tc(SCO) cycles
With qualifier 1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
7.9.4.3.2 External Interrupt Switching Characteristics (1)
PARAMETER MIN MAX UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.3.3 External Interrupt Timing Diagram
XNMI, XINT1, XINT2
tw(INT)
Interrupt Vector
td(INT)
Address bus
(internal)
Figure 7-15. External Interrupt Timing
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7.9.4.4 I2C Electrical Specification and Timing
7.9.4.4.1 I2C Timing
TEST CONDITIONS MIN MAX UNIT
fSCL SCL clock frequency
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
400 kHz
vil Low level input voltage 0.3 VDDIO V
Vih High level input voltage 0.7 VDDIO V
Vhys Input hysteresis 0.05 VDDIO V
Vol Low level output voltage 3-mA sink current 0 0.4 V
tLOW Low period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3 μs
tHIGH High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6 μs
lI
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX –10 10 μA
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7.9.4.5 Serial Peripheral Interface (SPI) Timing
This section contains both Master Mode and Slave Mode timing data.
7.9.4.5.1 Master Mode Timing
Section 7.9.4.5.1.1 lists the master mode timing (clock phase = 0) and Section 7.9.4.5.1.2 lists the master mode
timing (clock phase = 1). Figure 7-16 and Figure 7-17 show the timing waveforms.
7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
NO. PARAMETER BRR EVEN BRR ODD UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns
2 tw(SPC1)M
Pulse duration, SPICLK first
pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M + 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10 ns
3 tw(SPC2)M
Pulse duration, SPICLK second
pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
0.5tc(LSPCLK) + 10 ns
4 td(SIMO)M
Delay time, SPICLK to
SPISIMO valid 10 10 ns
5 tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK 0.5tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10 ns
8 tsu(SOMI)M
Setup time, SPISOMI before
SPICLK 20 20 ns
9 th(SOMI)M
Hold time, SPISOMI valid after
SPICLK 0 0 ns
23 td(SPC)M
Delay time, SPISTE active to
SPICLK tc(SPC)M – 10 0.5tc(SPC)M
0.5tc(LSPCLK) – 10 ns
24 td(STE)M
Delay time, SPICLK to SPISTE
inactive 0.5tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10 ns
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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I TEXAS INSTRUMENTS Higfi T“ w w x x x} x 4M 1 w \ \ \ w L4 \ \ 'WWWW — o‘wwwo"VW'o'o'o'wvo'o'o'wo' fofg’ofofofofoto‘ ’ofofofofofm‘oto’oofototofofofkiofofiofofofofg 1 * fl \ \ H—bk , \ v.7vvv.vvvv.v. l€.vvvv.vvvvv vvvvvv.vvvv.v.vvv 2.2222.2¢222.2.2¢ m:22.2.2222“.2¢222.22222.222¢2» 4F w‘P ¥
9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
8
Master Out Data Is Valid
3
2
1
SPISTE
5
23 24
Figure 7-16. SPI Master Mode External Timing (Clock Phase = 0)
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7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5)
NO. PARAMETER BRR EVEN BRR ODD UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns
2 tw(SPC1)M
Pulse duration, SPICLK first
pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M
0.5tc(LSPCLK) – 10
0.5tc(SPC)M
0.5tc(LSPCLK) + 10 ns
3 tw(SPC2)M
Pulse duration, SPICLK second
pulse 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 0.5tc(SPC)M +
0.5tc(LSPCLK) – 10
0.5tc(SPC)M +
0.5tc(LSPCLK) + 10 ns
6 td(SIMO)M
Delay time, SPISIMO valid to
SPICLK 0.5tc(SPC)M – 10 0.5tc(SPC)M +
0.5tc(LSPCLK) – 10 ns
7 tv(SIMO)M
Valid time, SPISIMO valid after
SPICLK 0.5tc(SPC)M – 10 0.5tc(SPC)M
0.5tc(LSPCLK) – 10 ns
10 tsu(SOMI)M
Setup time, SPISOMI before
SPICLK 20 20 ns
11 th(SOMI)M
Hold time, SPISOMI valid after
SPICLK 0 0 ns
23 td(SPC)M
Delay time, SPISTE active to
SPICLK tc(SPC) – 10 tc(SPC) – 10 ns
24 td(STE)M
Delay time, SPICLK to SPISTE
inactive 0.5tc(SPC) – 10 0.5tc(SPC)
0.5tc(LSPCLK) – 10 ns
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
11
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data Must
Be Valid
Master Out Data Is Valid
1
7
6
10
3
2
23 24
SPISTE
Figure 7-17. SPI Master Mode External Timing (Clock Phase = 1)
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7.9.4.5.2 Slave Mode Timing
Section 7.9.4.5.2.1 lists the slave mode timing (clock phase = 0) and Section 7.9.4.5.2.2 lists the slave mode
timing (clock phase = 1). Figure 7-18 and Figure 7-19 show the timing waveforms.
7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (4) (3) (5)
NO. PARAMETER MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK second pulse 2tc(SYSCLK) – 1 ns
15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 20 ns
16 tv(SOMI)S Valid time, SPISOMI data valid after SPICLK 0 ns
19 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns
20 th(SIMO)S Hold time, SPISIMO data valid after SPICLK 1.5tc(SYSCLK) ns
25 tsu(STE)S Setup time, SPISTE active before SPICLK 1.5tc(SYSCLK) ns
26 th(STE)S Hold time, SPISTE inactive after SPICLK 1.5tc(SYSCLK) ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
25
16
14
12
SPISTE
26
13
Figure 7-18. SPI Slave Mode External Timing (Clock Phase = 0)
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7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4)
NO. PARAMETER MIN MAX UNIT
12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK second pulse 2tc(SYSCLK) – 1 ns
17 td(SOMI)S Delay time, SPICLK to SPISOMI valid 20 ns
18 tv(SOMI)S Valid time, SPISOMI data valid after SPICLK 0 ns
21 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns
22 th(SIMO)S Hold time, SPISIMO data valid after SPICLK 1.5tc(SYSCLK) ns
25 tsu(STE)S Setup time, SPISTE active before SPICLK 1.5tc(SYSCLK) ns
26 th(STE)S Hold time, SPISTE inactive after SPICLK 1.5tc(SYSCLK) ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
21 18
17
SPISTE
Data ValidData Valid
14
13
12
25 26
Figure 7-19. SPI Slave Mode External Timing (Clock Phase = 1)
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