A Novel Twist: Maxim Integrated Removes Risk of RISC-V with a Dual-Core Arm/RISC-V Microcontroller

While Arm cores have proven themselves reliable and are now in most mobile devices and Internet of Things (IoT) endpoints, it’s always both useful and reassuring to have an alternative, as one size does not always fit all.

Enter the RISC-V 32-bit CPU. RISC-V (pronounced risk-five) is an open-source, no royalty architecture that is the first serious competition to the entrenched Arm CPU core ecosystem in a very long time. The base RV32 variant has 31 general-purpose, 32-bit registers named x1 to x31 (register x0 is hard-wired to 0). It supports extensions to the architecture that allow flexibility for different applications. For example, when building a microcontroller, the “B” RISC-V extension supports native bit manipulation, which in my long experience with microcontrollers is an indication that the architecture is serious about the deep embedded stuff.

The challenge, however, is getting engineers to accept a new architecture. It’s always a rocky road to adoption when you go against the existing sourcing momentum.

Maxim Integrated has solved this adoption problem by going in the direction of the sourcing momentum. The MAX78000EXG+ is a dual-core microcontroller with a 100 megahertz (MHz) Arm Cortex-M4 core with a floating-point unit (FPU) and a wide variety of serial communications interfaces. However, the Arm core shares the main bus with a second, 32-bit RISC-V core (Figure 1). The second core isn’t the only reason the MAX78000EXG+ is worth a closer look. The microcontroller has a 442 kilobyte (Kbyte) weight convolutional neural network (CNN) accelerator for artificial intelligence (AI) pattern matching. The RISC-V core is mainly there to act as a programmable smart direct memory access (DMA) to move data between the CNN and on-chip memory. However, the RISC-V core can also act independently, technically making the MAX78000EXG+ a dual-core processor.

Figure 1: The Maxim Integrated MAX78000EXG+ microcontroller has an Arm Cortex-M4 core with an FPU, alongside a RISC-V core. It also has a wide variety of serial interfaces, as well as a CNN for AI processing. (Image source: Maxim Integrated)

Now, I could do a comparison of the RISC-V and Arm architecture variants and ecosystems, but the raw truth is every time an engineering team sources a new microcontroller architecture not used by their employer, they are making a career decision. For example, a module maker risks having their product rejected by an integrator because the main core used in the product is not popular, or to use a more nebulous term “industry-accepted”. I saw this happen when I was with a semiconductor company and visiting a digital camera module manufacturer.

The company had built an impressive digital camera module based on a very niche digital signal processor (DSP), and when I write “niche”, I mean I estimated it had less than 10% of the DSP market. Regardless, the digital camera module had impressive statistics, and despite my deft PowerPoint and highly developed verbal communication skills, I could not persuade the module manufacturer to use my DSP—initially.

As it turned out, the digital camera integrators the module maker approached did not share their enthusiasm for the niche DSP. Despite its clear performance advantage, no camera integrators were willing to partner with the company and buy their module. The niche DSP core with its impressive specifications was too much of an unknown, and without sufficient market adoption, there was a concern that the DSP would be discontinued. After a quick recalibration, the module maker came back to me, and we ported their code to our DSP.

Another concern with sourcing a new core is that engineers just don’t have much experience—if any—with the architecture. In this situation, they can underestimate how the core can perform in their application, or what the real memory requirements are. Unlike sourcing a voltage regulator, it can take many months of development work, including the feature creep that often finds its way into the application, before it’s discovered that the selected core underperforms.

Maxim Integrated has apparently solved the engineering and business risks associated with sourcing the RISC-V core with the MAX78000EXG+. When not used as a smart DMA, the RISC-V core can be used as a second one in the application. Any concerns about performance are easily put to rest by the comforting presence of a Cortex-M4 and its nearby FPU.

Conclusion

Sourcing a new core such as the RISC-V can be ripe with uncertainty as to its performance in an application. Suitability for purpose and memory requirements are as yet unknown, and it can take months of coding before its capabilities are fully understood and appreciated. However, the Maxim Integrated MAX78000EXG+ has made it possible, in one of engineering’s great ironies, for an Arm core to reduce the technical and business concerns of adopting the RISC-V core in a new application.

關於作者

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Bill Giovino 是電子工程師,擁有美國雪城大學的電機工程學士學位,也是少數從設計工程師跨足現場應用工程師,再到技術行銷領域的成功典範之一。

Bill 過去 25 年來熱衷於向科技和非科技業的對象推廣新技術,包括 STMicroelectronics、Intel 和 Maxim Integrated 等多家企業。Bill 在 STMicroelectronics 任職期間,曾協助領導該公司順利進軍微控制器領域。在 Infineon 任職時,則策劃出該公司首款在美國汽車業大受歡迎的微控制器設計。Bill 目前是他個人公司 CPU Technologies 的行銷顧問,曾協助諸多企業讓表現不佳的產品重獲市場青睞。

Bill 更是採用物聯網的先驅,包括在微控制器中首次納入完整的 TCP/IP 堆疊。Bill 致力於推廣「用教育促成銷售」的理念,也認可在線上推銷產品時有清楚完整文字說明的重要性。他在 LikedIn 熱門的半導體銷售和行銷群組中擔任管理員,也擁有深厚的 B2E 知識。

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