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Configurable and Combination Logic Slide 3

Shown here is an example of how the 74LVC1G98 configurable logic device can be implemented as two separate functions, either a 2-input NAND gate, or a 2-input NOR gate. To implement the 74LVC1G98 as a NAND gate, the design engineer selects pins 3 and 6 as inputs, and pin 4 as the output. Pins 1 and 2 are tied to GND, while pin 5 is tied to VCC. The same 74LVC1G98 can be implemented as a NOR gate simply by selecting pins 1 and 6 as inputs, and pin 4 as the output. Pin 2 is tied to GND, while pins 3 and 5 are tied to VCC. The other seven available functions in the 74LVC1G98 are configured by different implementations of the pin configuration.

PTM Published on: 2014-02-06