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NexFET MOSFET Technology PTM Slide 16

This an actual picture of the power stage device. In the picture, the optimized driver IC is wire bonded to the external pins as well as connected to the low side FET on the bottom and the high side FET that is on top of the low side FET. The power stage also uses source-down stacked die architecture which reduces inductance and resistance between the devices like the power block.

PTM Published on: 2011-12-19