To design switches and multiplexers optimized for low capacitance performance, the die area must be kept to a minimum. This ensures very low parasitic capacitance because it is largely dependent on the switch area. Charge injection Q(inj) is the amount of charge coupled during switching from the digital input to the switch output. The amount of charge coupled to the switch output is a function of the gate-drain capacitance, so lower parasitic capacitance also minimizes Q(inj). However, the RON is inversely proportional to the die size, so the switch area should be as large as possible. As shown in this chart, there is a direct trade-off between RON and capacitance. A large die area, while providing low RON, means higher capacitance, higher Q(inj) and lower bandwidth. Larger die area also means more leakage and bigger package size.